On Mon, Dec 18, 2023 at 10:57 PM Daniel Henrique Barboza
<dbarb...@ventanamicro.com> wrote:
>
> 'svade' is a RVA22S64 profile requirement, a profile we're going to add
> shortly. It is a named feature (i.e. not a formal extension, not defined
> in riscv,isa DT at this moment) defined in [1] as:
>
> "Page-fault exceptions are raised when a page is accessed when A bit is
> clear, or written when D bit is clear.".
>
> As far as the spec goes, 'svade' is one of the two distinct modes of
> handling PTE_A and PTE_D. The other way, i.e. update PTE_A/PTE_D when
> they're cleared, is defined by the 'svadu' extension. Checking
> cpu_helper.c, get_physical_address(), we can verify that QEMU is
> compliant with that: we will update PTE_A/PTE_D if 'svadu' is enabled,
> or throw a page-fault exception if 'svadu' isn't enabled.
>
> So, as far as we're concerned, 'svade' translates to 'svadu must be
> disabled'.
>
> We'll implement it like 'zic64b': an internal flag that profiles can
> enable. The flag will not be exposed to users.
>
> [1] https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc
>
> Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajo...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 1 +
> target/riscv/cpu_cfg.h | 1 +
> target/riscv/tcg/tcg-cpu.c | 5 +++++
> 3 files changed, 7 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index a38d78b2d6..a76bc1b86a 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1445,6 +1445,7 @@ const RISCVCPUMultiExtConfig
> riscv_cpu_experimental_exts[] = {
> };
>
> const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
> + MULTI_EXT_CFG_BOOL("svade", svade, true),
> MULTI_EXT_CFG_BOOL("zic64b", zic64b, true),
>
> DEFINE_PROP_END_OF_LIST(),
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index 90f18eb601..46b06db68b 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -116,6 +116,7 @@ struct RISCVCPUConfig {
> bool ext_smepmp;
> bool rvv_ta_all_1s;
> bool rvv_ma_all_1s;
> + bool svade;
> bool zic64b;
>
> uint32_t mvendorid;
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 04aedf3840..e395e2449e 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -188,6 +188,9 @@ static void riscv_cpu_enable_named_feat(RISCVCPU *cpu,
> uint32_t feat_offset)
> cpu->cfg.cbop_blocksize = 64;
> cpu->cfg.cboz_blocksize = 64;
> break;
> + case CPU_CFG_OFFSET(svade):
> + cpu->cfg.ext_svadu = false;
> + break;
> default:
> g_assert_not_reached();
> }
> @@ -381,6 +384,8 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)
> cpu->cfg.zic64b = cpu->cfg.cbom_blocksize == 64 &&
> cpu->cfg.cbop_blocksize == 64 &&
> cpu->cfg.cboz_blocksize == 64;
> +
> + cpu->cfg.svade = !cpu->cfg.ext_svadu;
> }
>
> static void riscv_cpu_validate_g(RISCVCPU *cpu)
> --
> 2.43.0
>
>
