This series extracts fixes and refactorings that can be applied
independently from "[PATCH v9 00/23] plugins: Allow to read registers".
The patch "target/riscv: Move MISA limits to class" was replaced with
patch "target/riscv: Move misa_mxl_max to class" since I found instances
may have different misa_ext_mask.
V6 -> V7:
Rebased.
V5 -> V6:
Added patch "default-configs: Add TARGET_XML_FILES definition".
Rebased.
V4 -> V5:
Added patch "hw/riscv: Use misa_mxl instead of misa_mxl_max".
V3 -> V4:
Added patch "gdbstub: Check if gdb_regs is NULL".
V2 -> V3:
Restored patch sets from the previous version.
Rebased to commit 800485762e6564e04e2ab315132d477069562d91.
V1 -> V2:
Added patch "target/riscv: Do not allow MXL_RV32 for TARGET_RISCV64".
Added patch "target/riscv: Initialize gdb_core_xml_file only once".
Dropped patch "target/riscv: Remove misa_mxl validation".
Dropped patch "target/riscv: Move misa_mxl_max to class".
Dropped patch "target/riscv: Validate misa_mxl_max only once".
Signed-off-by: Akihiko Odaki <akihiko.od...@daynix.com>
---
Akihiko Odaki (4):
hw/riscv: Use misa_mxl instead of misa_mxl_max
target/riscv: Remove misa_mxl validation
target/riscv: Move misa_mxl_max to class
target/riscv: Validate misa_mxl_max only once
target/riscv/cpu.h | 4 +-
hw/riscv/boot.c | 2 +-
target/riscv/cpu.c | 139 ++++++++++++++++++++++++++-------------------
target/riscv/gdbstub.c | 12 ++--
target/riscv/kvm/kvm-cpu.c | 10 ++--
target/riscv/machine.c | 7 +--
target/riscv/tcg/tcg-cpu.c | 44 ++------------
target/riscv/translate.c | 3 +-
8 files changed, 109 insertions(+), 112 deletions(-)
---
base-commit: 9c74490bff6c8886a922008d0c9ce6cae70dd17e
change-id: 20231213-riscv-fcc9640986cf
Best regards,
--
Akihiko Odaki <akihiko.od...@daynix.com>
