Hi,
This new version contains changes proposed by Drew in v9. The most
notable change is the drop of the 'max' CPU profile restriction.
Patches based on Alistair's riscv-to-apply.next.
All patches acked.
- patch 3:
- move the 'priv_spec' comment to cpu_validate_multi_ext_priv_ver()
right before the version is bumped
- patch 4:
- Fixed 'Bare CPUs' comment in set_satp_mode_default_map()
- Changed rv64i_bare_cpu_init() comment to "Set to QEMU's first
supported priv version"
- patch 10:
- removed 'priv_spec' comment from cpu_set_profile()
- patch 18:
- added a DEFINE_PROFILE_CPU() macro
- renamed rva22u64_bare_cpu_init() to rva22u64_profile_cpu_init()
- patch 19: dropped
- v9 link:
https://lore.kernel.org/qemu-riscv/20231102224445.527355-1-dbarb...@ventanamicro.com/
Daniel Henrique Barboza (18):
target/riscv: create TYPE_RISCV_VENDOR_CPU
target/riscv/tcg: do not use "!generic" CPU checks
target/riscv/tcg: update priv_ver on user_set extensions
target/riscv: add rv64i CPU
target/riscv: add zicbop extension flag
target/riscv/tcg: add 'zic64b' support
riscv-qmp-cmds.c: expose named features in cpu_model_expansion
target/riscv: add rva22u64 profile definition
target/riscv/kvm: add 'rva22u64' flag as unavailable
target/riscv/tcg: add user flag for profile support
target/riscv/tcg: add MISA user options hash
target/riscv/tcg: add riscv_cpu_write_misa_bit()
target/riscv/tcg: handle profile MISA bits
target/riscv/tcg: add hash table insert helpers
target/riscv/tcg: honor user choice for G MISA bits
target/riscv/tcg: validate profiles during finalize
riscv-qmp-cmds.c: add profile flags in cpu-model-expansion
target/riscv: add 'rva22u64' CPU
hw/riscv/virt.c | 5 +
target/riscv/cpu-qom.h | 4 +
target/riscv/cpu.c | 134 ++++++++++++-
target/riscv/cpu.h | 13 ++
target/riscv/cpu_cfg.h | 3 +
target/riscv/kvm/kvm-cpu.c | 7 +-
target/riscv/riscv-qmp-cmds.c | 44 ++++-
target/riscv/tcg/tcg-cpu.c | 350 ++++++++++++++++++++++++++++++----
8 files changed, 507 insertions(+), 53 deletions(-)
--
2.41.0
