On Oct 25 11:14, Cédric Le Goater wrote: > Cc: Klaus > > On 9/21/23 05:48, Andrew Jeffery wrote: > > It appears some (many?) EEPROMs that implement 16-bit data addressing > > will accept an 8-bit address and clock out non-uniform data for the > > read. This behaviour is exploited by an EEPROM detection routine in part > > of OpenBMC userspace with a reasonably broad user base: > > > > https://github.com/openbmc/entity-manager/blob/0422a24bb6033605ce75479f675fedc76abb1167/src/fru_device.cpp#L197-L229 > > > > The diversity of the set of EEPROMs that it operates against is unclear, > > but this code has been around for a while now. > > > > Separately, The NVM Express Management Interface Specification dictates > > the provided behaviour in section 8.2 Vital Product Data: > > > > > If only one byte of the Command Offset is provided by the Management > > > Controller, then the least significant byte of the internal offset > > > shall be set to that value and the most-significant byte of the > > > internal offset shall be cleared to 0h > > > > https://nvmexpress.org/wp-content/uploads/NVM-Express-Management-Interface-Specification-1.2c-2022.10.06-Ratified.pdf > > > > This change makes it possible to expose NVMe VPD in a manner that can be > > dynamically detected by OpenBMC. > > > > Signed-off-by: Andrew Jeffery <and...@codeconstruct.com.au> > > It seems that the "at24c-eeprom" model doesn't have a maintainer. Until > this is sorted out, may be this change could go through the NVMe queue > since it is related. >
I can, but I'm not that confident on determining if we choose to implement this behavior broadly. I have no qualms, but someone who works more with embedded stuff might?
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