[Qemu-devel] [PATCH] PXA-specific ARM hacks.

[andrzej zaborowski]

This patch contains some ugly but very useful chnages:
- in cpu-exec.c, halt the arm CPU on CPU_INTERRUPT_HALT like in other
architectures.
- wake the cpu up on CPU_INTERRUPT_EXITTB - this serves waking the
CPU up without asserting IRQ or FIQ, which is possible on PXA. Would
it be better to add a separate interrupt type instead?
- in target-arm/translate.c, don't terminate the TB after a CP15
write. The purpose of this is to imitate the real processor's
instruction cache (to some degree). OSes should never need rely on the
cache prefetch but unfortunately Linux for pxa does when it's waking
up from sleep or deep idle, when enabling the MMU (simplifies things a
lot for Linux).

Cheers,
Andrew

From 7ba76bd146394be87dc6480a172386a9e5e73877 Mon Sep 17 00:00:00 2001
From: Andrzej Zaborowski <[EMAIL PROTECTED]>
Date: Fri, 16 Mar 2007 17:25:41 +0100
Subject: [PATCH] PXA-specific ARM hacks.

---
 cpu-all.h              |    3 ++-
 cpu-exec.c             |   10 ++++++++--
 target-arm/translate.c |    2 ++
 3 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/cpu-all.h b/cpu-all.h
index 9b617fc..177bcba 100644
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -763,7 +763,8 @@ void cpu_dump_statistics (CPUState *env, FILE *f,
                           int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
                           int flags);
 
-void cpu_abort(CPUState *env, const char *fmt, ...);
+void cpu_abort(CPUState *env, const char *fmt, ...)
+    __attribute__ ((__format__ (__printf__, 2, 3)));
 extern CPUState *first_cpu;
 extern CPUState *cpu_single_env;
 extern int code_copy_enabled;
diff --git a/cpu-exec.c b/cpu-exec.c
index 48c2a93..2e99de2 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -276,8 +276,8 @@ int cpu_exec(CPUState *env1)
     if (env1->halted) {
         /* An interrupt wakes the CPU even if the I and F CPSR bits are
            set.  */
-        if (env1->interrupt_request
-            & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
+        if (env1->interrupt_request &
+            (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB)) {
             env1->halted = 0;
         } else {
             return EXCP_HALTED;
@@ -528,6 +528,12 @@ int cpu_exec(CPUState *env1)
                         env->exception_index = EXCP_IRQ;
                         do_interrupt(env);
                     }
+                    if (interrupt_request & CPU_INTERRUPT_HALT) {
+                        env->interrupt_request &= ~CPU_INTERRUPT_HALT;
+                        env->halted = 1;
+                        env->exception_index = EXCP_HLT;
+                        cpu_loop_exit();
+                    }
 #elif defined(TARGET_SH4)
                    /* XXXXX */
 #endif
diff --git a/target-arm/translate.c b/target-arm/translate.c
index e5032c5..c476e06 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -1536,7 +1536,9 @@ static int disas_cp15_insn(DisasContext *s, uint32_t insn)
         gen_movl_T0_reg(s, rd);
         gen_op_movl_cp15_T0(insn);
     }
+#if 0
     gen_lookup_tb(s);
+#endif
     return 0;
 }
 
-- 
1.4.4.3


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