There is a bug in the ARM emulation of data-processing instructions with
ASR <reg> when the shift==0. The current QEMU CVS incorrectly modifies
the C-flag, when it should be preserved.
The attached patch corrects this.
Matthew
Index: target-arm/op.c
===================================================================
RCS file: /sources/qemu/qemu/target-arm/op.c,v
retrieving revision 1.21
diff -u -r1.21 op.c
--- target-arm/op.c 26 Jun 2006 19:55:19 -0000 1.21
+++ target-arm/op.c 11 Feb 2007 16:08:22 -0000
@@ -667,7 +667,7 @@
if (shift >= 32) {
env->CF = (T1 >> 31) & 1;
T1 = (int32_t)T1 >> 31;
- } else {
+ } else if (shift != 0) {
env->CF = (T1 >> (shift - 1)) & 1;
T1 = (int32_t)T1 >> shift;
}
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