This patch was created by Martin Bochnig ([EMAIL PROTECTED]) and is for qemu compiling on sparc to work on arm, mips, and sparc binaries, dealing with the sparc register allocation issues.
diff -ruN qemu-ORIG/target-arm/exec.h qemu/target-arm/exec.h --- qemu-ORIG/target-arm/exec.h 2005-11-26 05:38:39.000000000 -0500 +++ qemu/target-arm/exec.h 2007-01-20 02:36:04.000000000 -0500 @@ -19,10 +19,17 @@ */ #include "dyngen-exec.h" +#if defined(__sparc__) +struct CPUARMState *env; +uint32_t T0; +uint32_t T1; +uint32_t T2; +#else register struct CPUARMState *env asm(AREG0); register uint32_t T0 asm(AREG1); register uint32_t T1 asm(AREG2); register uint32_t T2 asm(AREG3); +#endif /* TODO: Put these in FP regs on targets that have such things. */ /* It is ok for FT0s and FT0d to overlap. Likewise FT1s and FT1d. */ diff -ruN qemu-ORIG/target-mips/exec.h qemu/target-mips/exec.h --- qemu-ORIG/target-mips/exec.h 2007-01-23 20:47:51.000000000 -0500 +++ qemu/target-mips/exec.h 2007-01-30 16:27:20.000000000 -0500 @@ -7,7 +7,11 @@ #include "mips-defs.h" #include "dyngen-exec.h" +#if defined(__sparc__) +struct CPUMIPSState *env; +#else register struct CPUMIPSState *env asm(AREG0); +#endif #if defined (USE_64BITS_REGS) typedef int64_t host_int_t; @@ -17,6 +21,11 @@ typedef uint32_t host_uint_t; #endif +#if defined(__sparc__) +host_uint_t T0; +host_uint_t T1; +host_uint_t T2; +#else #if TARGET_LONG_BITS > HOST_LONG_BITS #define T0 (env->t0) #define T1 (env->t1) @@ -26,6 +35,7 @@ register host_uint_t T1 asm(AREG2); register host_uint_t T2 asm(AREG3); #endif +#endif #if defined (USE_HOST_FLOAT_REGS) #error "implement me." diff -ruN qemu-ORIG/target-sparc/exec.h qemu/target-sparc/exec.h --- qemu-ORIG/target-sparc/exec.h 2005-10-30 13:16:26.000000000 -0500 +++ qemu/target-sparc/exec.h 2007-01-20 02:36:04.000000000 -0500 @@ -3,23 +3,41 @@ #include "dyngen-exec.h" #include "config.h" +#if defined(__sparc__) +struct CPUSPARCState *env; +#else register struct CPUSPARCState *env asm(AREG0); +#endif + #ifdef TARGET_SPARC64 #define T0 (env->t0) #define T1 (env->t1) #define T2 (env->t2) #define REGWPTR env->regwptr #else +#if defined(__sparc__) +register uint32_t T0 asm(AREG3); +register uint32_t T1 asm(AREG2); +#else register uint32_t T0 asm(AREG1); register uint32_t T1 asm(AREG2); +#endif #undef REG_REGWPTR // Broken #ifdef REG_REGWPTR +#if defined(__sparc__) +register uint32_t *REGWPTR asm(AREG4); +#else register uint32_t *REGWPTR asm(AREG3); +#endif #define reg_REGWPTR #ifdef AREG4 +#if defined(__sparc__) +register uint32_t T2 asm(AREG0); +#else register uint32_t T2 asm(AREG4); +#endif #define reg_T2 #else #define T2 (env->t2) @@ -27,7 +45,11 @@ #else #define REGWPTR env->regwptr +#if defined(__sparc__) +register uint32_t T2 asm(AREG0); +#else register uint32_t T2 asm(AREG3); +#endif #define reg_T2 #endif #endif
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