On Thu, Jan 11, 2007 at 09:00:58PM +0100, Fabrice Bellard wrote:
> I would prefer to keep the PIIX3 for the PC until the PIIX4 is more
> tested (and implemented !). I would accept having both PIIX3 and PIIX4
> (a flag could suffice at the init).
>
Please find below a new patch. I have actually implemented it by copying
the code, as I have found after sedning the previous one that some other
PCI registers should have different values. That's currently the case of
the PCI IRQ routing registers (0x60 to 0x63) and maybe some other
registers in the future.
Cheers,
Aurelien
This patch adds the 82371EB PCI-to-ISA bridge. This device is needed
for the Malta platform and cannot be replaced by the 82371SB as there
are some specific PCI fixups in the Linux kernel. However there are
very few differences with the 82371SB, so this device could eventually
be used for the i386 and x86_64 targets. Note however that the PCI IRQ
are not routed exactly the same way, but that should not hurt the later
platforms.
diff -Nurd qemu.orig/hw/piix_pci.c qemu/hw/piix_pci.c
--- qemu.orig/hw/piix_pci.c 2007-01-10 17:23:41.000000000 +0100
+++ qemu/hw/piix_pci.c 2007-01-11 22:14:19.000000000 +0100
@@ -197,6 +197,7 @@ PCIBus *i440fx_init(PCIDevice **pi440fx_
/* PIIX3 PCI to ISA bridge */
PCIDevice *piix3_dev;
+PCIDevice *piix4_dev;
/* just used for simpler irq handling. */
#define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32)
@@ -259,6 +260,44 @@ static void piix3_reset(PCIDevice *d)
pci_conf[0xae] = 0x00;
}
+static void piix4_reset(PCIDevice *d)
+{
+ uint8_t *pci_conf = d->config;
+
+ pci_conf[0x04] = 0x07; // master, memory and I/O
+ pci_conf[0x05] = 0x00;
+ pci_conf[0x06] = 0x00;
+ pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
+ pci_conf[0x4c] = 0x4d;
+ pci_conf[0x4e] = 0x03;
+ pci_conf[0x4f] = 0x00;
+ pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
+ pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
+ pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
+ pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
+ pci_conf[0x69] = 0x02;
+ pci_conf[0x70] = 0x80;
+ pci_conf[0x76] = 0x0c;
+ pci_conf[0x77] = 0x0c;
+ pci_conf[0x78] = 0x02;
+ pci_conf[0x79] = 0x00;
+ pci_conf[0x80] = 0x00;
+ pci_conf[0x82] = 0x00;
+ pci_conf[0xa0] = 0x08;
+ pci_conf[0xa0] = 0x08;
+ pci_conf[0xa2] = 0x00;
+ pci_conf[0xa3] = 0x00;
+ pci_conf[0xa4] = 0x00;
+ pci_conf[0xa5] = 0x00;
+ pci_conf[0xa6] = 0x00;
+ pci_conf[0xa7] = 0x00;
+ pci_conf[0xa8] = 0x0f;
+ pci_conf[0xaa] = 0x00;
+ pci_conf[0xab] = 0x00;
+ pci_conf[0xac] = 0x00;
+ pci_conf[0xae] = 0x00;
+}
+
static void piix_save(QEMUFile* f, void *opaque)
{
PCIDevice *d = opaque;
@@ -296,3 +335,27 @@ int piix3_init(PCIBus *bus, int devfn)
piix3_reset(d);
return d->devfn;
}
+
+int piix4_init(PCIBus *bus, int devfn)
+{
+ PCIDevice *d;
+ uint8_t *pci_conf;
+
+ d = pci_register_device(bus, "PIIX4", sizeof(PCIDevice),
+ devfn, NULL, NULL);
+ register_savevm("PIIX4", 0, 2, piix_save, piix_load, d);
+
+ piix4_dev = d;
+ pci_conf = d->config;
+
+ pci_conf[0x00] = 0x86; // Intel
+ pci_conf[0x01] = 0x80;
+ pci_conf[0x02] = 0x10; // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge
+ pci_conf[0x03] = 0x71;
+ pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
+ pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
+ pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
+
+ piix4_reset(d);
+ return d->devfn;
+}
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' [EMAIL PROTECTED] | [EMAIL PROTECTED]
`- people.debian.org/~aurel32 | www.aurel32.net
_______________________________________________
Qemu-devel mailing list
Qemu-devel@nongnu.org
http://lists.nongnu.org/mailman/listinfo/qemu-devel
