[The previous patch had a broken MIPS32R2 bitops implementation, and was apparently too big to make it to the list. I retry now with a compressed attachment.]
Hello All, this patch adds support for all mandatory MIPS32R2 instructions, rationalizes the instruction decoding to check always 32-bit words, reduces the number of magic constants in the code, adds a few bits which make eventually implementation of MIPS64 support and optional MIPS32 features easier. The emulated CPU still identifies itself as a MIPS32(R1) 4Kc. Currently it doesn't throw a RI exception for R2 instructions, this is useful for Linux userland emulation, and also follows the current policy which doesn't distinguish between MIPS32R1 instructions and those of earlier ISAs. Thiemo
opcode-handling.gz
Description: Binary data
_______________________________________________ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
