On Tuesday 31 October 2006 2:02 pm, Paul Brook wrote: > As an example take the arm instruction > > add, r0, r1, r2, lsl #2 > > This is equivalent to the C expression > > r0 = r1 + (r2 << 2) ... > When fully converted to the new system this would become: > > int tmp = gen_new_qreg(); /* Allocate a temporary reg. */ > /* gen_im32 is a helper that allocates a new qreg and > initializes it to an immediate value. */ > gen_op_add32(tmp, QREG_R2, gen_im32(2)); > gen_op_add32(QREG_R0, QREG_R1, tmp);
I forgot to ask: Where's the shift? I think the above code means you generate an immediate value (the 2), add it to R2 with the result going in a spill register, and then add the spill register to R1, with the result going to R0. Should that middle line be some kind of gen_op_lshift32() instead of gen_op_add32()? Do qregs ever get freed? (I'm guessing gen_new_qreg() lasts until the end of the translated block, and then the next block has its own set of qregs?) Rob -- "Perfection is reached, not when there is no longer anything to add, but when there is no longer anything to take away." - Antoine de Saint-Exupery _______________________________________________ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
