Fabrice Bellard wrote: > Thiemo Seufer wrote: > >Fabrice Bellard wrote: > > > >>CVSROOT: /sources/qemu > >>Module name: qemu > >>Branch: > >>Changes by: Fabrice Bellard <[EMAIL PROTECTED]> 06/05/02 > >>22:18:28 > >> > >>Modified files: > >> hw : mips_r4k.c > >> > >>Log message: > >> performance boost (on P4 hosts at least, rdtsc is a _very_ bad > >> random generator) > >> > >>CVSWeb URLs: > >>http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/hw/mips_r4k.c.diff?tr1=1.15&tr2=1.16&r1=text&r2=text > > > > > >Does this really provide a measurable performance improvement? > >Real hardware simply increments cp0_random together with the cycle > >counter, this is randomized enough for TLB entry replacement. > > Unfortunately, at least on my P4 PC it is not random enough: it is > always a multiple of two, so the number of TLBs is divided by two ! The > speed improvement is _very_ noticeable. > > Your patch to accelerate tlb_flush_page() is still interesting, but I > would like to be sure that it does not reduce the speed of the x86 > target. In particular, it could be possible to make it even faster by > reducing the size of the memset by using a smarter hash for tb_jmp_cache > (a few bit of the index could depend only on the memory page number).
As interim solution I moved it to mips specific code, I still don't trust the MIPS TLB handling that much since it starts to fail once I remove seemingly unnecessary flushes. I still have nearly no time to work on qemu ATM. :-( Thiemo _______________________________________________ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
