> -----Original Message----- > From: Paul Brook [mailto:[EMAIL PROTECTED] > Sent: Tuesday, March 14, 2006 3:21 PM > To: qemu-devel@nongnu.org > Cc: Schwarz, Konrad > Subject: Re: [Qemu-devel] Questions on ARM port > > > Basically, r3 is initialized by <start+8> (to 0x80000, in > my case). > > The next instruction (at <start+12>) switches the mode to > FIQ. After > > single steping over this in QEMU (via GDB si), r3 no longer > contains > > what it had before (0x80000), instead, it is set to 0. If > I manually > > fix this (via set $r3=0x80000), then at the next mode switch (at > > <start+28>) r3 is changed incorrectly to zero again. > > > > Is this my fault or what is happening? > > It's a big in the qemu FIQ bank switching code. Fixed now. > > Paul
Oh, great! How do I get the patch? Konrad _______________________________________________ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
