On Thursday 12 May 2005 23:13, Pascal Terjan wrote:
> On 5/12/05, Paul Brook <[EMAIL PROTECTED]> wrote:
> > On Wednesday 11 May 2005 22:04, Paul Brook wrote:
> > > The attached patch adds support for gcc4 x86 and x86_64 hosts.
> >
> > This time with the correct patch attached.
>
> Hello, I can't build qemu under gcc4.0.0 with your patch and using -O2.
> I get :
> /home/pterjan/rpm/BUILD/qemu-0.7.0/target-i386/ops_sse.h: In function
> 'op_pshufw_mmx':
> /home/pterjan/rpm/BUILD/qemu-0.7.0/target-i386/ops_sse.h:574: error:
> unable to find a register to spill in class 'GENERAL_REGS'
> /home/pterjan/rpm/BUILD/qemu-0.7.0/target-i386/ops_sse.h:574: error:
> this is the insn:
> (insn:HI 18 17 19 0
> /home/pterjan/rpm/BUILD/qemu-0.7.0/target-i386/ops_sse.h:569 (set
> (strict_low_part (subreg:HI (reg/v:DI 63 [ r ]) 0))
> (mem/s/j:HI (plus:SI (mult:SI (reg:SI 64)
> (const_int 2 [0x2]))
> (reg/v/f:SI 59 [ s ])) [0 <variable>._w S2 A16])) 41
> {*movstricthi_1} (insn_list:REG_DEP_TRUE 16 (insn_list:REG_DEP_TRUE 12
> (insn_list:REG_DEP_TRUE 53 (nil))))
> (expr_list:REG_DEAD (reg:SI 64)
> (nil)))
> /home/pterjan/rpm/BUILD/qemu-0.7.0/target-i386/ops_sse.h:574: confused
> by earlier errors, bailing out
This is a gcc bug. See gcc.gnu.org/PR16185.
Basically gcc doesn't like doing 64-bit arithmetic on a target with only three
32-bit registers (We use the other 4 registers to hold the guest CPU state).
You can hack around this by not holding the guest cpu state in registers, but
this incurs a significant speed penalty.
Paul
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