I'm trying to extract module contents from Verilog, which has the form
of;
module foo (port1, port2, ... );
// module contents to extract here.
...
endmodule
To extract the module contents, I'm planning to do something like;
from pyparsing import *
ident = Word(alphas+"_", alphanums+"_")
module_begin = Group("module" + ident + "(" + OneOrMore(ident) + ")" + ";")
module_contents = ???
module_end = Keyword("endmodule")
module = Group(module_begin + module_contents + module_end)
(abobe code not tested.)
How should I write the part of 'module_contents'? It's an arbitrary text
which doesn't contain 'endmodule' keyword. I don't want to use full
scale Verilog parser for this task.
-Inyeol
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