On Mon, Nov 28, 2005 at 09:00:58PM +0000, Paul McGuire wrote:
> "Inyeol Lee" <[EMAIL PROTECTED]> wrote in message
> [...]
> > How should I write the part of 'module_contents'? It's an arbitrary text
> > which doesn't contain 'endmodule' keyword. I don't want to use full
> > scale Verilog parser for this task.
> >
> > -Inyeol
>
> The simplest way is to use SkipTo. This only works if you don't have to
> worry about nesting. I think Verilog supports nested modules, but if the
> files you are parsing don't use this feature, then SkipTo will work just
> fine.
>
> module_begin = Group("module" + ident + "(" + OneOrMore(ident) + ")" + ";")
> module_end = Keyword("endmodule")
> module_contents = SkipTo(module_end)
>
> If you *do* care about nested modules, then a parse action might help you
> handle these cases. But this starts to get trickier, and you may just want
> to consider a more complete grammar. If your application is non-commercial
> (i.e., for academic or personal use), there *is* a full Verilog grammar
> available (also available with commercial license, just not free).
>
> -- Paul
Thanks Paul. 'SkipTo' is what I was looking for.
-Inyeol
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