> I have been evaluating the python environment ever more closer. I > believe I can interface python with a development environment known as > the ImpulseC environment. The ImpulseC environment develops C to VHDL > for FPGA development. I would especially love to interface Python > with ImpulseC and the graphing capabilities of GNU Plot and SciPy in > order to recreate a VHDL development environment that will be just as > capable as a $50,000 dollar Matlab to VHDL toolbox. This is also a part > of my Masters thesis. Is anyone willing to help in this endeavor????? > > David Blubaugh >
Why not use MyHDL which is written in Python and translates to Verilog. I assume ImpulseC is a commercial product and costs a log. MyHDL is free. If you have any interests in combining MyHDL with SciPy and NumPy I would be interested in getting involved. Dan Fabrizio -- http://mail.python.org/mailman/listinfo/python-list
