On Thu, May 30, 2019 at 08:44:43PM +0200, Mark Kettenis wrote: > > https://cvsweb.openbsd.org/cgi-bin/cvsweb/~checkout~/src/sys/arch/powerpc/powerpc/cpu_subr.c?rev=1.8&content-type=text/plain > > > > I could see a mtmsrd being called on a G4 then if I didn't know any better, > > and those were 32-bit processors right? > > > > Let me know if I'm misreading this code, > > I think you are. For the G5 the code is essentially overwriting all > rfi instructions with rfid instructions. On G4 and earlier the code > is overwriting the sequences that use the mtmsrd instruction with > nop instructions.
They are patching the instructions. Cool! If I can bug you one more time on something. I see a lot of mtmsrd opcodes then in locore.S that aren't followed with an immediate isync opcode. Isn't that needed? I'm looking at trapcode() near nop32_1e: In section 2.3.16 of "Programming Environments Manual for 64-bit Micro- processors" it talks about it, I think I have a copy of it here: https://centroid.eu/enhancedrisc/pem_64bit_v3.0.2005jul15.pdf If not I don't want to take up too much of your time. In fact I kept a low profile on asking questions anyhow since you guys are generally overloaded with work. > Anyway, all I wanted to do is give a heads-up to say that this stuff > can be quite non-intuitive. Especially the how the bits move around > between the 32-bit and 64-bit representation of the msr register on > the G5. This isn't helped by the way IBM numbers bits from zero for > the most-significant bit. I know what you mean. Like in that same hyperlinked document section 2.3.1. Best Regards, -peter
