> From: Ralph Siegler <rsieg...@rsiegler.org>
> Date: Wed, 2 Jul 2014 00:39:37 +0000 (UTC)
> 
> The display on this emac goes blank right at the end of booting, even 
> though display works fine from bsd.rd
> 
> 
> Not using X and answered "No" to expecting to use X during install.
> 
> Now emac with radeon is not in the list of supported machines, however 
> since things do work from bsd.rd I was wondering if there was any setting 
> I could "knock out" to just get basic console?

disabling radeondrm should work; see config(8) for details

I've just committed the diff below, which might help (but probably
doesn't).  More likely some changes are necessary in radeon_combios.c,
in particular in radeon_get_legacy_connector_info_from_table().  As
you can see, your model (PowerMac6,4) isn't listed there.  It might be
worth trying to map your "PowerMac6,4" to CT_MINI_INTERNAL or
CT_MINI_EXTERNAL in that function and see if that makes things work.


Index: radeon_clocks.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/drm/radeon/radeon_clocks.c,v
retrieving revision 1.1
diff -u -p -r1.1 radeon_clocks.c
--- radeon_clocks.c     12 Aug 2013 04:11:53 -0000      1.1
+++ radeon_clocks.c     2 Jul 2014 18:47:02 -0000
@@ -32,6 +32,10 @@
 #include "radeon.h"
 #include "atom.h"
 
+#if defined(__macppc__) || defined(__sparc64__)
+#include <dev/ofw/openfirm.h>
+#endif
+
 uint32_t        radeon_legacy_get_engine_clock(struct radeon_device *);
 uint32_t        radeon_legacy_get_memory_clock(struct radeon_device *);
 void            radeon_legacy_set_engine_clock(struct radeon_device *, 
uint32_t);
@@ -96,6 +100,8 @@ uint32_t radeon_legacy_get_memory_clock(
        return mclk;
 }
 
+#ifdef __linux__
+
 #ifdef CONFIG_OF
 /*
  * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
@@ -176,6 +182,84 @@ static bool radeon_read_clocks_OF(struct
        return false;
 }
 #endif /* CONFIG_OF */
+
+#else
+
+#if defined(__macppc__) || defined(__sparc64__)
+/*
+ * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
+ * tree. Hopefully, ATI OF driver is kind enough to fill these
+ */
+static bool radeon_read_clocks_OF(struct drm_device *dev)
+{
+       struct radeon_device *rdev = dev->dev_private;
+       int node = PCITAG_NODE(rdev->pa_tag);
+       uint32_t val;
+       struct radeon_pll *p1pll = &rdev->clock.p1pll;
+       struct radeon_pll *p2pll = &rdev->clock.p2pll;
+       struct radeon_pll *spll = &rdev->clock.spll;
+       struct radeon_pll *mpll = &rdev->clock.mpll;
+
+       if (OF_getprop(node, "ATY,RefCLK", &val, sizeof(val)) != sizeof(val) || 
!val)
+               return false;
+       p1pll->reference_freq = p2pll->reference_freq = (val) / 10;
+       p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
+       if (p1pll->reference_div < 2)
+               p1pll->reference_div = 12;
+       p2pll->reference_div = p1pll->reference_div;
+
+       /* These aren't in the device-tree */
+       if (rdev->family >= CHIP_R420) {
+               p1pll->pll_in_min = 100;
+               p1pll->pll_in_max = 1350;
+               p1pll->pll_out_min = 20000;
+               p1pll->pll_out_max = 50000;
+               p2pll->pll_in_min = 100;
+               p2pll->pll_in_max = 1350;
+               p2pll->pll_out_min = 20000;
+               p2pll->pll_out_max = 50000;
+       } else {
+               p1pll->pll_in_min = 40;
+               p1pll->pll_in_max = 500;
+               p1pll->pll_out_min = 12500;
+               p1pll->pll_out_max = 35000;
+               p2pll->pll_in_min = 40;
+               p2pll->pll_in_max = 500;
+               p2pll->pll_out_min = 12500;
+               p2pll->pll_out_max = 35000;
+       }
+       /* not sure what the max should be in all cases */
+       rdev->clock.max_pixel_clock = 35000;
+
+       spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;
+       spll->reference_div = mpll->reference_div =
+               RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
+                           RADEON_M_SPLL_REF_DIV_MASK;
+
+       if (OF_getprop(node, "ATY,SCLK", &val, sizeof(val)) == sizeof(val) && 
val)
+               rdev->clock.default_sclk = (val) / 10;
+       else
+               rdev->clock.default_sclk =
+                       radeon_legacy_get_engine_clock(rdev);
+
+       if (OF_getprop(node, "ATY,MCLK", &val, sizeof(val)) == sizeof(val) && 
val)
+               rdev->clock.default_mclk = (val) / 10;
+       else
+               rdev->clock.default_mclk =
+                       radeon_legacy_get_memory_clock(rdev);
+
+       DRM_INFO("Using device-tree clock info\n");
+
+       return true;
+}
+#else
+static bool radeon_read_clocks_OF(struct drm_device *dev)
+{
+       return false;
+}
+#endif /* CONFIG_OF */
+
+#endif
 
 void radeon_get_clock_info(struct drm_device *dev)
 {

Reply via email to