On Sun, 04 Jan 2004 17:53, Dan Sugalski wrote;
> Given that it's not a SMP, massively out of order NUMA system with > delayed writes... no. 'Fraid not.
Sorry to be pedantic, but I always thought that the NU in NUMA implied a contradiction of the S in SMP!
"NUMA MP" or "SMP", what does it mean to have *both* ?
It means you've got loosely coupled clusters of SMP things. For an example, if you go buy an Alpha GS3200 32 processor system (assuming DEC^WCompaq^HP still knows how to sell the things) you have one of these things. It's a set of 8 4-processor nodes with a fast interconnect between them which functions as a 32 CPU system. The four processors in each node are in a traditional SMP setup with a shared memory bus, tightly coupled caches, and fight-for-the-bus access to the memory on that node. Access to memory on another node goes over a slower bus, though it still looks and acts like local memory.
Nearly all of the NUMA systems I know of act like this, because it's still feasible to have tightly coupled 2 or 4 CPU SMP systems. The global slowdown generally occurs past that point, so the NUMA systems usually group 2 or 4 CPU SMP systems together this way.
Given the increases in processor vs memory vs bus speeds, this setup may not hold for that much longer, as it's only really workable when a single CPU doesn't saturate the memory bus with any regularity, which is getting harder and harder to do. (backplane and memory speeds can be increased pretty significantly with a sufficient application of cash, which is why the mini and mainframe systems can actually do it, but there are limits beyond which cash just won't get you)
--
Dan
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Dan Sugalski even samurai
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