> Michelle, > > > Description > > > > x86 APIC scalability project will modify low-level > > > Solaris interrupt handling mechanism to > support > > 256 * #CPUs on a multi-processor system. > The project > > will also support multiple interrupt > priority level on > > the same IRQ and unfixed interrupts at > every priority > > level. > > > > Related Projects > > > > It is a dependency for IRM (interrupt resource > management) > > x86 implementation. > > > > References: > > Project proposal: > > > http://greatwall.prc/~xc151355/x86_apic/x86_apic_propo > sal.txt > > (The document will be posted to community once the > proposal is approved.) > > I'm not willing to approve this until your > documentation is posted in a > location where anyone in the community may read it. > The proposal isn't > arked Sun/Internal. > Just posted the original text.
> I would reccomend that the proposal be expanded for > those of us who > aren't familiar with Interrupt Resource Management > and x86 APIC issues. See if the following can help. > Just off the top of my head, I'm curious about the > following issues: > > a) Is there a design document for IRM. It would be > nice to see how > these projects fit together. The IRM project was just approved at the device driver and ON community but the project hasnt been set up so the project docs have been posted. http://www.opensolaris.org/jive/thread.jspa?threadID=101375&tstart=0 http://mail.opensolaris.org/pipermail/on-discuss/2009-April/000852.html Again, internal website is here if it helps. http://pice.sfbay/intr > b) The APIC is x86 specific. Are there SPARC > interrupt scalability > issues? How are these being addressed. SPARC doesnt have this issue. > c) The proposal doesn't include any evidence to > support your claim that > there is an APIC scalability problem. Would you > please provide > performance data and analysis that shows where the > current bottlenecks > are, and how your approach might solve the problem. The later pasted proposal text has more description on the current issues. Please see if that explains. This project only provides a larger interrupt pool. It is up to how the interrupts are used by other components (ie drivers/NUMA/IRM) for system throughput improvement. Thanks Michelle > > Thanks, > > -j > > _______________________________________________ > perf-discuss mailing list > perf-discuss@opensolaris.org -- This message posted from opensolaris.org _______________________________________________ perf-discuss mailing list perf-discuss@opensolaris.org
