Michelle, > Description > > x86 APIC scalability project will modify low-level > Solaris interrupt handling mechanism to support > 256 * #CPUs on a multi-processor system. The project > will also support multiple interrupt priority level on > the same IRQ and unfixed interrupts at every priority > level. > > Related Projects > > It is a dependency for IRM (interrupt resource management) > x86 implementation. > > References: > Project proposal: > http://greatwall.prc/~xc151355/x86_apic/x86_apic_proposal.txt > (The document will be posted to community once the proposal is approved.)
I'm not willing to approve this until your documentation is posted in a location where anyone in the community may read it. The proposal isn't marked Sun/Internal. I would reccomend that the proposal be expanded for those of us who aren't familiar with Interrupt Resource Management and x86 APIC issues. Just off the top of my head, I'm curious about the following issues: a) Is there a design document for IRM. It would be nice to see how these projects fit together. b) The APIC is x86 specific. Are there SPARC interrupt scalability issues? How are these being addressed. c) The proposal doesn't include any evidence to support your claim that there is an APIC scalability problem. Would you please provide performance data and analysis that shows where the current bottlenecks are, and how your approach might solve the problem. Thanks, -j _______________________________________________ perf-discuss mailing list perf-discuss@opensolaris.org
