On Wed, Oct 05, 2005 at 08:53:17AM -0700, David McDaniel (damcdani) wrote: | Are the sparc TLBs transparent as to instrucitons or data? At one | point I though I read that I and D tlbs were separate entities.
I'm only talking about the SPARC DTLB here, since that is what you were concerned with. The SPARC ITLBs are 128-256 entries for USIII+/USIV/USIV+ and are only capable of handling 8K mappings (64K programmable on USIV+). The fully associative 16 entry ITLB ends up holding larger text pages when they are in use. The Opterons as well as the sun4v SPARC CPUs have a unified TLB architecture (some sun4v CPUs have separate I/D micro TLBs but they are invisible outside the CPU pipeline). - Eric -- Eric Lowe Solaris Kernel Development Austin, Texas Sun Microsystems. We make the net work. x64155/+1(512)401-1155 _______________________________________________ perf-discuss mailing list perf-discuss@opensolaris.org
