[PATCH 1/2] ath79: correct switch PHYs for GMAC0 in ar934x

[Randy Li via openwrt-devel]

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According to Ethernet Subsystem section of Functional Description
chapter of the datasheet, when GMAC0 connects to the internal
switch, it is MDC/MDIO of the GMAC0 decided which PHY it should
talk to.

Signed-off-by: Randy Li <ay...@soulik.info>
---
 target/linux/ath79/dts/ar934x.dtsi | 31 +++++++++++++++---------------
 1 file changed, 16 insertions(+), 15 deletions(-)

diff --git a/target/linux/ath79/dts/ar934x.dtsi 
b/target/linux/ath79/dts/ar934x.dtsi
index 94dfde4125..69393ac8c5 100644
--- a/target/linux/ath79/dts/ar934x.dtsi
+++ b/target/linux/ath79/dts/ar934x.dtsi
@@ -229,7 +229,22 @@
 };
 
 &mdio0 {
+       status = "okay";
+
        compatible = "qca,ar9340-mdio";
+
+       swphy0: ethernet-phy@0 {
+               reg = <0>;
+               phy-mode = "mii";
+               status = "disabled";
+       };
+
+       swphy4: ethernet-phy@4 {
+               reg = <4>;
+               phy-mode = "mii";
+               status = "disabled";
+       };
+
 };
 
 &eth0 {
@@ -244,6 +259,7 @@
        clock-names = "eth", "mdio";
 };
 
+/* AR9342 has no internal switch */
 &mdio1 {
        status = "okay";
 
@@ -261,21 +277,6 @@
                phy-mode = "gmii";
                qca,mib-poll-interval = <500>;
                qca,phy4-mii-enable;
-
-               mdio-bus {
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-
-                       swphy0: ethernet-phy@0 {
-                               reg = <0>;
-                               phy-mode = "mii";
-                       };
-
-                       swphy4: ethernet-phy@4 {
-                               reg = <4>;
-                               phy-mode = "mii";
-                       };
-               };
        };
 };
 
-- 
2.41.0

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