From: Sven Eckelmann <sven.eckelm...@open-mesh.com> Signed-off-by: Sven Eckelmann <sven.eckelm...@open-mesh.com> --- v2: - Split into multiple patches and adjust slightly to look more like an OpenWrt patch
.../601-MIPS-ath79-add-more-register-defines.patch | 32 +++++++++++++++++++++- .../601-MIPS-ath79-add-more-register-defines.patch | 32 +++++++++++++++++++++- 2 files changed, 62 insertions(+), 2 deletions(-) diff --git a/target/linux/ar71xx/patches-4.1/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-4.1/601-MIPS-ath79-add-more-register-defines.patch index ae44285..213195c 100644 --- a/target/linux/ar71xx/patches-4.1/601-MIPS-ath79-add-more-register-defines.patch +++ b/target/linux/ar71xx/patches-4.1/601-MIPS-ath79-add-more-register-defines.patch @@ -217,7 +217,7 @@ #define AR71XX_GPIO_COUNT 16 #define AR7240_GPIO_COUNT 18 #define AR7241_GPIO_COUNT 20 -@@ -560,4 +671,235 @@ +@@ -560,4 +671,265 @@ #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 @@ -452,4 +452,34 @@ +#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3 +#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20 + ++#define QCA955X_GMAC_REG_SGMII_RESET 0x14 ++ ++#define QCA955X_SGMII_RESET_HW_RX_125M BIT(4) ++#define QCA955X_SGMII_RESET_TX_125M BIT(3) ++#define QCA955X_SGMII_RESET_RX_125M BIT(2) ++#define QCA955X_SGMII_RESET_TX_CLK BIT(1) ++#define QCA955X_SGMII_RESET_RX_CLK BIT(0) ++ ++#define QCA955X_GMAC_REG_MR_AN_CONTROL 0x1c ++ ++#define QCA955X_MR_AN_CONTROL_PHY_RESET BIT(15) ++#define QCA955X_MR_AN_CONTROL_LOOPBACK BIT(14) ++#define QCA955X_MR_AN_CONTROL_SPEED_SEL0 BIT(13) ++#define QCA955X_MR_AN_CONTROL_AN_ENABLE BIT(12) ++#define QCA955X_MR_AN_CONTROL_POWER_DOWN BIT(11) ++#define QCA955X_MR_AN_CONTROL_RESTART_AN BIT(9) ++#define QCA955X_MR_AN_CONTROL_DUPLEX_MODE BIT(8) ++#define QCA955X_MR_AN_CONTROL_SPEED_SEL1 BIT(6) ++ ++#define QCA955X_GMAC_REG_SGMII_DEBUG 0x58 ++ ++#define QCA955X_SGMII_DEBUG_ARB_STATE_MASK 0xf ++#define QCA955X_SGMII_DEBUG_ARB_STATE_SHIFT 24 ++#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_MASK 0xff ++#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_SHIFT 16 ++#define QCA955X_SGMII_DEBUG_RX_STATE_MASK 0xff ++#define QCA955X_SGMII_DEBUG_RX_STATE_SHIFT 8 ++#define QCA955X_SGMII_DEBUG_TX_STATE_MASK 0xff ++#define QCA955X_SGMII_DEBUG_TX_STATE_SHIFT 0 ++ #endif /* __ASM_MACH_AR71XX_REGS_H */ diff --git a/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch index ae44285..213195c 100644 --- a/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch +++ b/target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch @@ -217,7 +217,7 @@ #define AR71XX_GPIO_COUNT 16 #define AR7240_GPIO_COUNT 18 #define AR7241_GPIO_COUNT 20 -@@ -560,4 +671,235 @@ +@@ -560,4 +671,265 @@ #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 @@ -452,4 +452,34 @@ +#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3 +#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20 + ++#define QCA955X_GMAC_REG_SGMII_RESET 0x14 ++ ++#define QCA955X_SGMII_RESET_HW_RX_125M BIT(4) ++#define QCA955X_SGMII_RESET_TX_125M BIT(3) ++#define QCA955X_SGMII_RESET_RX_125M BIT(2) ++#define QCA955X_SGMII_RESET_TX_CLK BIT(1) ++#define QCA955X_SGMII_RESET_RX_CLK BIT(0) ++ ++#define QCA955X_GMAC_REG_MR_AN_CONTROL 0x1c ++ ++#define QCA955X_MR_AN_CONTROL_PHY_RESET BIT(15) ++#define QCA955X_MR_AN_CONTROL_LOOPBACK BIT(14) ++#define QCA955X_MR_AN_CONTROL_SPEED_SEL0 BIT(13) ++#define QCA955X_MR_AN_CONTROL_AN_ENABLE BIT(12) ++#define QCA955X_MR_AN_CONTROL_POWER_DOWN BIT(11) ++#define QCA955X_MR_AN_CONTROL_RESTART_AN BIT(9) ++#define QCA955X_MR_AN_CONTROL_DUPLEX_MODE BIT(8) ++#define QCA955X_MR_AN_CONTROL_SPEED_SEL1 BIT(6) ++ ++#define QCA955X_GMAC_REG_SGMII_DEBUG 0x58 ++ ++#define QCA955X_SGMII_DEBUG_ARB_STATE_MASK 0xf ++#define QCA955X_SGMII_DEBUG_ARB_STATE_SHIFT 24 ++#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_MASK 0xff ++#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_SHIFT 16 ++#define QCA955X_SGMII_DEBUG_RX_STATE_MASK 0xff ++#define QCA955X_SGMII_DEBUG_RX_STATE_SHIFT 8 ++#define QCA955X_SGMII_DEBUG_TX_STATE_MASK 0xff ++#define QCA955X_SGMII_DEBUG_TX_STATE_SHIFT 0 ++ #endif /* __ASM_MACH_AR71XX_REGS_H */ -- 2.8.0.rc3 _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
