NAK, xway is a unified kernel target and we wont change that upstream. i am fine with the cpu override bit but i wont take the KConfig part,
sorry, John On 01/07/2014 02:37, José Vázquez Fernández wrote: > This draft adds cpu-feature-overrides.h using the FALCON one as > base. Due to the different cores used in ASE and Danube the Kconfig > was modified to disable some options that are present in the AR9 > and VR9 SoCs, like multithreading, mt ASE and some others. > According with UGW all the Lantiq SoCs supported in OpenWRT have > CPU_MIPSR2_IRQ_VI but it was not tested nor added. FALCON sets > cpu_has_vint and cpu_has_veic to 1, but here were left undefined > because i have no idea if the XWAY family have and/or support > they. Due to only dcdc driver only has effect with the VR9 the > Makefile was modified to include it only when SOC_XWAY is > selected. > > As a side effect the kernel size is 30KB smaller. > > This patch, as is, works fine with a Danube based router, but, as i > have said, is only a draft that, if it has interest, must be > improved. > > José Vázquez > > > > diff -urN > a/arch/mips/include/asm/mach-lantiq/xway/cpu-feature-overrides.h > b/arch/mips/include/asm/mach-lantiq/xway/cpu-feature-overrides.h > --- > a/arch/mips/include/asm/mach-lantiq/xway/cpu-feature-overrides.h > 1970-01-01 01:00:00.000000000 +0100 +++ > b/arch/mips/include/asm/mach-lantiq/xway/cpu-feature-overrides.h > 2014-07-01 01:34:41.980432797 +0200 @@ -0,0 +1,67 @@ +/* + * > Lantiq XWAY specific CPU feature overrides + * + * This file was > derived from: include/asm-mips/cpu-features.h + * Copyright (C) > 2003, 2004 Ralf Baechle + * Copyright (C) 2004 Maciej W. > Rozycki + * + * This program is free software; you can > redistribute it and/or modify it + * under the terms of the GNU > General Public License version 2 as published + * by the Free > Software Foundation. + * + */ +#ifndef > __ASM_MACH_XWAY_CPU_FEATURE_OVERRIDES_H +#define > __ASM_MACH_XWAY_CPU_FEATURE_OVERRIDES_H + +#define cpu_has_tlb > 1 +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 > +#define cpu_has_4k_cache 1 +#define cpu_has_tx39_cache 0 > +#define cpu_has_sb1_cache 0 +#define cpu_has_fpu 0 > +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 > +#define cpu_has_watch 1 +#define cpu_has_divec 1 + > +#define cpu_has_prefetch 1 +#define cpu_has_ejtag 1 > +#define cpu_has_llsc 1 + +#if > defined(CONFIG_SOC_AMAZON_SE) +#define cpu_has_mips16 0 > +#endif + +#define cpu_has_mdmx 0 +#define cpu_has_mips3d > 0 +#define cpu_has_smartmips 0 +#define cpu_has_vz 0 + > +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 1 > +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + > +#if defined(CONFIG_SOC_AMAZON_SE) +#define cpu_has_dsp 0 > +#endif + +#define cpu_has_dsp2 0 + +#if > defined(CONFIG_SOC_AMAZON_SE) || defined(CONFIG_SOC_DANUBE) > +#define cpu_has_mipsmt 0 +#endif + +//#define cpu_has_vint > ? /* MIPSR2 vectored interrupts */ +//#define cpu_has_veic ? > /* MIPSR2 external interrupt controller mode */ + +#define > cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 > +#define cpu_has_64bit_gp_regs 0 +#define > cpu_has_64bit_addresses 0 + +#define cpu_dcache_line_size() > 32 +#define cpu_icache_line_size() 32 + +#endif /* > __ASM_MACH_XWAY_CPU_FEATURE_OVERRIDES_H */ diff -urN > a/arch/mips/Kconfig b/arch/mips/Kconfig --- a/arch/mips/Kconfig > 2014-07-01 01:11:21.000000000 +0200 +++ b/arch/mips/Kconfig > 2014-06-30 23:59:30.000000000 +0200 @@ -241,7 +241,6 @@ select > SYS_HAS_CPU_MIPS32_R2 select SYS_SUPPORTS_BIG_ENDIAN select > SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_MULTITHREADING > select SYS_HAS_EARLY_PRINTK select ARCH_REQUIRE_GPIOLIB select > SWAP_IO_SPACE diff -urN a/arch/mips/lantiq/Kconfig > b/arch/mips/lantiq/Kconfig --- a/arch/mips/lantiq/Kconfig > 2014-07-01 01:11:23.000000000 +0200 +++ b/arch/mips/lantiq/Kconfig > 2014-07-01 01:17:23.592775282 +0200 @@ -11,14 +11,21 @@ default > SOC_XWAY > > config SOC_AMAZON_SE - bool "Amazon SE" + bool "XWAY Amazon > SE" select SOC_TYPE_XWAY > > +config SOC_DANUBE + bool "XWAY Danube" + select > SOC_TYPE_XWAY + select HW_HAS_PCI + select ARCH_SUPPORTS_MSI > + config SOC_XWAY - bool "XWAY" + bool "XWAY Danube, AR9 and > VR9" select SOC_TYPE_XWAY select HW_HAS_PCI select > ARCH_SUPPORTS_MSI + select SYS_SUPPORTS_MULTITHREADING > > config SOC_FALCON bool "FALCON" @@ -31,12 +38,12 @@ > > config DT_EASY50712 bool "Easy50712" - depends on SOC_XWAY + > depends on SOC_XWAY || SOC_DANUBE endchoice > > config PCI_LANTIQ bool "PCI Support" - depends on SOC_XWAY && > PCI + depends on (SOC_XWAY || SOC_DANUBE) && PCI > > config PCIE_LANTIQ bool "PCIE Support" diff -urN > a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile > --- a/arch/mips/lantiq/xway/Makefile 2014-07-01 > 01:11:23.000000000 +0200 +++ b/arch/mips/lantiq/xway/Makefile > 2014-07-01 02:02:33.946247244 +0200 @@ -1,8 +1,9 @@ -obj-y := > prom.o sysctrl.o clk.o reset.o dma.o timer.o dcdc.o +obj-y := > prom.o sysctrl.o clk.o reset.o dma.o timer.o > > obj-y += vmmc.o mtd_split.o tffs.o > > obj-y += eth_mac.o obj-$(CONFIG_PCI) += ath_eep.o rt_eep.o > pci-ath-fixup.o +obj-$(CONFIG_SOC_XWAY) += dcdc.o > > obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o diff -urN > a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig --- > a/drivers/gpio/Kconfig 2014-07-01 01:11:23.000000000 +0200 +++ > b/drivers/gpio/Kconfig 2014-07-01 01:38:04.421147758 +0200 @@ > -142,7 +142,7 @@ > > config GPIO_MM_LANTIQ bool "Lantiq Memory mapped GPIOs" - > depends on LANTIQ && SOC_XWAY + depends on LANTIQ && (SOC_XWAY > || SOC_DANUBE) help This enables support for memory mapped GPIOs on > the External Bus Unit (EBU) found on Lantiq SoCs. The gpios are > output only as they are @@ -446,7 +446,7 @@ > > config GPIO_STP_XWAY bool "XWAY STP GPIOs" - depends on > SOC_XWAY + depends on SOC_XWAY || SOC_DANUBE help This enables > support for the Serial To Parallel (STP) unit found on XWAY SoC. > The STP allows the SoC to drive a shift registers cascade, > _______________________________________________ openwrt-devel > mailing list openwrt-devel@lists.openwrt.org > https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel > _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel