On Wed, Jan 8, 2014 at 10:04 PM, dani <dgcb...@gmail.com> wrote: > Currently the parameter MIPS_L1_CACHE_SHIFT defaults to 5 , but should be 4. > > MIPS_L1_CACHE_SHIFT = 5 matches to a cache linesize of 32 bytes, but BCM63xx > SoCs use cores with > 16 bytes linesize and therefore should be MIPS_L1_CACHE_SHIFT = 4. > This parameter is used by the compiler for some alignment in vmlinux.lds and > by the SLAB allocator.
Nice catch. I don't see this upstream though, please submit it to linux-m...@linux-mips.org so it will be fixed in linux itself. I will then pick it up for OpenWrt. Regards Jonas _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
