Currently the parameter MIPS_L1_CACHE_SHIFT defaults to 5 , but should be 4.
MIPS_L1_CACHE_SHIFT = 5 matches to a cache linesize of 32 bytes, but BCM63xx
SoCs use cores with
16 bytes linesize and therefore should be MIPS_L1_CACHE_SHIFT = 4.
This parameter is used by the compiler for some alignment in vmlinux.lds and by
the SLAB allocator.
Signed-off-by: Daniel Gonzalez <dgcb...@gmail.com>
Index:
target/linux/brcm63xx/patches-3.10/121-MIPS-BCM63XX-MIPS_L1_CACHE_SHIFT.patch
===================================================================
---
target/linux/brcm63xx/patches-3.10/121-MIPS-BCM63XX-MIPS_L1_CACHE_SHIFT.patch
(revision 0)
+++
target/linux/brcm63xx/patches-3.10/121-MIPS-BCM63XX-MIPS_L1_CACHE_SHIFT.patch
(working copy)
@@ -0,0 +1,11 @@
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -1164,7 +1164,7 @@
+
+ config MIPS_L1_CACHE_SHIFT
+ int
+- default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL ||
SOC_RT288X
++ default "4" if BCM63XX || MACH_DECSTATION || MIKROTIK_RB532 ||
PMC_MSP4200_EVAL || SOC_RT288X
+ default "6" if MIPS_CPU_SCACHE
+ default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM ||
CPU_CAVIUM_OCTEON
+ default "5"
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