05.11.2012, 22:56, "Daniel Golle" <dgo...@allnet.de>:
> Hi!
>
> On 05/11/12 16:16, Сергей Василюгин wrote:
>
>> While porting to dlink DIR-620 D1 (rt3352) I see that ralink driver
>> (ftp://ftp.dlink.ru/pub/Router/DIR-620/Source/gpl_DIR_620D1.tar.gz):
>> - toggles rf02 before initing RF (like rt3290, rt5390, rt5392 in
>> rt2800lib.c);
>> - use different rf_vals if Xtal 20MHz (checked by SYSC_REG_SYSTEM_CONFIG
>> & (1<<20) -> 0 = 20MHz, 1 = 40MHz).
>> After patching these and ap_type netif_carrier wifi works, LEDs don't (with
>> vendor firmware too :)).
>
> Good to hear that! Thank you for the effort!
> Did you test on the DIR-620 itself?
>
>> So two questions:
>> 1. Are these patches not so critical? Or I don't understand something.
>
> Probably just not relevant for the ALL5002 system-in-a-module and where
> missing
> in the reference driver I had access to.
> Or I overlooked something, the more eye-pairs, the more you see :)
>
>> 2. LEDs work?
>
> The SoM we got exposes all GPIOs to the user, and gpio-leds seems to work in
> that way. I got no idea if OR/AND'ing a GPIO with a WiFi-hardware-trigger
> works
> (I saw that such a feature seems to exist in the vendor driver)
>
> Please share your patch so I can test it on my hardware as well.
> I suggest that once we tested it on both our Rt3352F-based gear, you should
> post
> the patch to be included in OpenWrt mac80211/patches and simultanously also
> post
> on the rt2x00-users mailing list. Once it got ack'ed by some rt2x00
> maintainer,
> re-post it on linux-wireless so it can go into wireless-testing and then
> linux-next...
>
> Thank you for the review and the testing!
>
> Best regards
>
> Daniel
Thanks for your answer.
Patch to test included.
---
serge
--- rt2800lib.c.orig 2012-10-06 00:08:10.000000000 +0700
+++ rt2800lib.c 2012-11-07 22:12:43.000000000 +0600
@@ -2272,10 +2272,15 @@
* Change BBP settings
*/
if (rt2x00_rt(rt2x00dev, RT3352)) {
+ rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
+ rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
+ rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
rt2800_bbp_write(rt2x00dev, 27, 0x0);
rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
rt2800_bbp_write(rt2x00dev, 27, 0x20);
rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
+ rt2800_bbp_write(rt2x00dev, 86, 0x38);
+ rt2800_bbp_write(rt2x00dev, 83, 0x6a);
} else {
rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
@@ -3850,6 +3855,7 @@
* Init RF calibration.
*/
if (rt2x00_rt(rt2x00dev, RT3290) ||
+ rt2x00_rt(rt2x00dev, RT3352) ||
rt2x00_rt(rt2x00dev, RT5390) ||
rt2x00_rt(rt2x00dev, RT5392)) {
rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
@@ -4036,6 +4042,15 @@
rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
return 0;
} else if (rt2x00_rt(rt2x00dev, RT3352)) {
+ int tx0_int_pa = 1, tx1_int_pa = 1; /*tx0 tx1 internel/external PA*/
+
+ rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
+ if( eeprom != 0xffff) {
+ if(eeprom & (1<<14)) tx0_int_pa = 0;
+ if(eeprom & (1<<15)) tx1_int_pa = 0;
+ printk("rf3322:tx0_int_pa=%d tx1_int_pa=%d\n",tx0_int_pa, tx1_int_pa);
+ }
+
rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
@@ -4069,15 +4084,16 @@
rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
- rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
+ rfcsr = 0x01 | (tx0_int_pa ? 0x00 : 0x04 ) | (tx1_int_pa ? 0x00 : 0x08 ) ;
+ rt2800_rfcsr_write(rt2x00dev, 34, rfcsr );
rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
- rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
- rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
+ rt2800_rfcsr_write(rt2x00dev, 41, (tx0_int_pa ? 0x5b : 0x52) );
+ rt2800_rfcsr_write(rt2x00dev, 42, (tx1_int_pa ? 0x5b : 0x52) );
rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
@@ -4085,15 +4101,16 @@
rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
- rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
- rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
- rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
- rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
- rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
- rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
- rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
- rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
- rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
+ rfcsr = 0x2d | (tx0_int_pa ? 0x00 : 0x07 ) | (tx1_int_pa ? 0x00 : 0x07<<3 ) ;
+ rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
+ rt2800_rfcsr_write(rt2x00dev, 51, (tx0_int_pa ? 0x7f : 0x52) );
+ rt2800_rfcsr_write(rt2x00dev, 52, (tx0_int_pa ? 0x00 : 0xc0) );
+ rt2800_rfcsr_write(rt2x00dev, 53, (tx0_int_pa ? 0x52 : 0xd2) );
+ rt2800_rfcsr_write(rt2x00dev, 54, (tx0_int_pa ? 0x1b : 0xc0) );
+ rt2800_rfcsr_write(rt2x00dev, 55, (tx1_int_pa ? 0x7f : 0x52) );
+ rt2800_rfcsr_write(rt2x00dev, 56, (tx1_int_pa ? 0x00 : 0xc0) );
+ rt2800_rfcsr_write(rt2x00dev, 57, (tx0_int_pa ? 0x52 : 0x49) );
+ rt2800_rfcsr_write(rt2x00dev, 58, (tx1_int_pa ? 0x1b : 0xc0) );
rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
@@ -5027,6 +5044,27 @@
{173, 0x61, 0, 9},
};
+/*
+ * RF value list for rt3xxx with Xtal20MHz
+ * Supports: 2.4 GHz (all) (RF3322)
+ */
+static const struct rf_channel rf_vals_xtal20mhz_3x[] = {
+ {1, 0xE2, 2, 0x14},
+ {2, 0xE3, 2, 0x14},
+ {3, 0xE4, 2, 0x14},
+ {4, 0xE5, 2, 0x14},
+ {5, 0xE6, 2, 0x14},
+ {6, 0xE7, 2, 0x14},
+ {7, 0xE8, 2, 0x14},
+ {8, 0xE9, 2, 0x14},
+ {9, 0xEA, 2, 0x14},
+ {10, 0xEB, 2, 0x14},
+ {11, 0xEC, 2, 0x14},
+ {12, 0xED, 2, 0x14},
+ {13, 0xEE, 2, 0x14},
+ {14, 0xF0, 2, 0x18},
+};
+
static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
{
struct hw_mode_spec *spec = &rt2x00dev->spec;
@@ -5104,7 +5142,6 @@
rt2x00_rf(rt2x00dev, RF3022) ||
rt2x00_rf(rt2x00dev, RF3290) ||
rt2x00_rf(rt2x00dev, RF3320) ||
- rt2x00_rf(rt2x00dev, RF3322) ||
rt2x00_rf(rt2x00dev, RF5360) ||
rt2x00_rf(rt2x00dev, RF5370) ||
rt2x00_rf(rt2x00dev, RF5372) ||
@@ -5112,6 +5149,19 @@
rt2x00_rf(rt2x00dev, RF5392)) {
spec->num_channels = 14;
spec->channels = rf_vals_3x;
+ } else if (rt2x00_rf(rt2x00dev, RF3322)) {
+ /* serge: need check if it's specific for all SoCs or rt3352 or rf3322 or my board dlink dir-620d1
+ so separated if
+ */
+ int syscfg = (*((volatile u32 *)(/* RT305X_SYSC_BASE */ 0xb0000000 + /* SYSC_REG_SYSTEM_CONFIG */ 0x10)));
+
+ spec->num_channels = 14;
+ if( syscfg & (1<<20) )
+ spec->channels = rf_vals_3x;
+ else {
+ spec->channels = rf_vals_xtal20mhz_3x;
+ printk("rf3322:Use xtal 20MHz\n");
+ }
} else if (rt2x00_rf(rt2x00dev, RF3052)) {
spec->supported_bands |= SUPPORT_BAND_5GHZ;
spec->num_channels = ARRAY_SIZE(rf_vals_3x);
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