v2, use mdelay not for loop
Lantiq ethernet and builtin phy on amazon se (ase)
fix CFG, IGPLEN register addresses
add extra CFG settings
enable etop <-> ephy connection
reset ephy
some delays seemed to help.
Signed-off-by: Conor O'Gorman <i...@conorogorman.net>
---
.../patches-3.2/301-fix-etop-for-ase-ephy.patch | 61 ++++++++++++++++++++
1 files changed, 61 insertions(+), 0 deletions(-)
create mode 100644
target/linux/lantiq/patches-3.2/301-fix-etop-for-ase-ephy.patch
diff --git a/target/linux/lantiq/patches-3.2/301-fix-etop-for-ase-ephy.patch
b/target/linux/lantiq/patches-3.2/301-fix-etop-for-ase-ephy.patch
new file mode 100644
index 0000000..ed59d2c
--- /dev/null
+++ b/target/linux/lantiq/patches-3.2/301-fix-etop-for-ase-ephy.patch
@@ -0,0 +1,61 @@
+--- a/drivers/net/ethernet/lantiq_etop.c
++++ b/drivers/net/ethernet/lantiq_etop.c
+@@ -59,8 +59,8 @@
+ #define LTQ_ETOP_ENETS0 0x11850
+ #define LTQ_ETOP_MAC_DA0 0x1186C
+ #define LTQ_ETOP_MAC_DA1 0x11870
+-#define LTQ_ETOP_CFG 0x16020
+-#define LTQ_ETOP_IGPLEN 0x16080
++#define LTQ_ETOP_CFG 0x11808
++#define LTQ_ETOP_IGPLEN 0x11820
+
+ #define MAX_DMA_CHAN 0x8
+ #define MAX_DMA_CRC_LEN 0x4
+@@ -73,7 +73,9 @@
+ #define ETOP_PLEN_UNDER 0x40
+ #define ETOP_CGEN 0x800
+ #define ETOP_CFG_MII0 0x01
+-
++#define ETOP_CFG_EPHY 0x4000
++#define ETOP_CFG_FEN 0x100
++#define ETOP_CFG_SEN 0x40
+ #define LTQ_GBIT_MDIO_CTL 0xCC
+ #define LTQ_GBIT_MDIO_DATA 0xd0
+ #define LTQ_GBIT_GCTL0 0x68
+@@ -148,6 +150,7 @@ struct ltq_etop_priv {
+
+ static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
+ int phy_reg, u16 phy_data);
++static int ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg);
+
+ static int
+ ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
+@@ -348,11 +351,25 @@ ltq_etop_hw_init(struct net_device *dev)
+
+ default:
+ if (ltq_is_ase()) {
++ int i;
++ /* disconnect */
++ ltq_etop_w32(ETOP_CFG_MII0, LTQ_ETOP_CFG);
++
++ /* enable clk/pwr to ephy */
+ clk_enable(priv->clk_ephy);
+- /* disable external MII */
+- ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
+- /* enable clock for internal PHY */
+ clk_enable(priv->clk_ephycgu);
++ mdelay(10);
++
++ /* enable ephy connection, fen and sen, only */
++ ltq_etop_w32(
++ ETOP_CFG_EPHY | ETOP_CFG_FEN | ETOP_CFG_SEN,
++ LTQ_ETOP_CFG);
++ mdelay(10);
++
++ /* reset */
++ ltq_etop_mdio_wr(NULL, 8, 0, 0x80);
++ mdelay(10);
++
+ /* we need to write this magic to the internal phy to
+ make it work */
+ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
--
1.7.4.1
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