On 06/04/12 14:37, Conor O'Gorman wrote: > ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG); > +- /* enable clock for internal PHY */ > + clk_enable(priv->clk_ephycgu); > ++ for (i = 0; i < 0x50000; i++); > ++ > ++ /* enable ephy connection, fen and sen, only */ > ++ ltq_etop_w32( > ++ ETOP_CFG_EPHY | ETOP_CFG_FEN | ETOP_CFG_SEN, > ++ LTQ_ETOP_CFG); > ++ for (i = 0; i < 0x50000; i++);
Hi, assuming a loop needs 8 op codes and you are running at 333mhz we get roughly 8 miliseconds can you try with a mdelay(5 or 10) ? Thanks, John _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
