I've an idea... On Fri, Oct 22, 2010 at 5:56 AM, Helmut Schaa <helmut.sc...@googlemail.com> wrote: > Hi, > > CC'ed rt2x00 list ... > > Am Donnerstag 21 Oktober 2010 schrieb Scott Nicholas: >> On Thu, Oct 21, 2010 at 12:25 PM, Helmut Schaa >> <helmut.sc...@googlemail.com> wrote: >> > I fully agree. The same also applies to rt2800pci SoCs (rt305x) which are >> > working quite good already (in terms of WiFi) but also show more CPU usage >> > then the legacy drivers. >> > >> > IMO it would really make sense to work on improving rt2x00 & mac80211 >> > instead >> > of putting much work in a maybe-better-behaving but unmaintainable driver. >> > >> > For example you could start by profiling rt61pci (if your platform supports >> > perf counters) to see if you can find any obvious bottlenecks. >> >> My platform SoC is MIPS32 4Kc core which does not seem to do >> profiling... I wonder if some reports made on different machine would >> help steer me in the correct direction, and if anyone has access to >> rt61pci that could do this.. > > I don't have a rt61pci card but since it shares a lot of base code with > rt2800pci we should be able to find some suitable starting points. > > Ivo, any ideas (or starting points) what we could do to improve CPU usage > in rt2x00 on embedded systems? > > Thanks, > Helmut >
I haven't looked at much code lately, have been busy. But I wanted to replace u-boot on my router with netconsole enabled. My ethernet is similar to DEC21140-pci and Linksys/Infineon copied that driver and changed little. netconsole doesn't work, and tftp transfers have always taken a couple timeouts before they start. I've also been skipping around in the book "See MIPS Run" and yesterday found a DEC21140 datasheet to decode the TX status descriptor. The issue here is that the packet DMA address is physical, and nowhere is the cache flushed/write-backed or whatever. So it spins in a loop waiting for the packet to transmit, and it'll timeout, then enter the send routine again later and loop another million times and hopefully for some odd reason the memory has been written and it works the 2nd-3rd time. I wonder then, if this is similar issue for rt61pci. Since it's primary target would be x86 and their DMA is completely coherent, eh? This wouldn't probably explain the performance on the RDC/i486 clone that Florian mentioned though, and I am not very educated at the low-level workings of such things, but that's what I came up with. -- scott _______________________________________________ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
