Hi Florian,
I've updated the spi driver, it fixes the following issues :
- chipselect
- command register defines
- add missing clock
Kind regards,
Tanguy Bouzéloc.
>From e99254247409e97b8976221517ef65419389d887 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tanguy=20Bouz=C3=A9loc?= <tanguy.bouze...@efixo.com>
Date: Thu, 18 Nov 2010 16:19:17 +0100
Subject: [PATCH] fix chipselect, command register defines, add missing clock
---
target/linux/brcm63xx/patches-2.6.35/240-spi.patch | 30 +++++++++++++------
1 files changed, 20 insertions(+), 10 deletions(-)
diff --git a/target/linux/brcm63xx/patches-2.6.35/240-spi.patch
b/target/linux/brcm63xx/patches-2.6.35/240-spi.patch
index ed35e36..c2dc79c 100644
--- a/target/linux/brcm63xx/patches-2.6.35/240-spi.patch
+++ b/target/linux/brcm63xx/patches-2.6.35/240-spi.patch
@@ -122,7 +122,7 @@
+
+static struct bcm63xx_spi_pdata spi_pdata = {
+ .bus_num = 0,
-+ .num_chipselect = 8,
++ .num_chipselect = 4,
+ .speed_hz = 50000000, /* Fclk */
+};
+
@@ -273,10 +273,10 @@
+#define SPI_MSG_TYPE_SHIFT 14
+
+/* Command */
-+#define SPI_CMD_NOOP 0x01
-+#define SPI_CMD_SOFT_RESET 0x02
-+#define SPI_CMD_HARD_RESET 0x04
-+#define SPI_CMD_START_IMMEDIATE 0x08
++#define SPI_CMD_NOOP 0x00
++#define SPI_CMD_SOFT_RESET 0x01
++#define SPI_CMD_HARD_RESET 0x02
++#define SPI_CMD_START_IMMEDIATE 0x03
+#define SPI_CMD_COMMAND_SHIFT 0
+#define SPI_CMD_COMMAND_MASK 0x000f
+#define SPI_CMD_DEVICE_ID_SHIFT 4
@@ -318,7 +318,7 @@
#endif /* BCM63XX_REGS_H_ */
--- /dev/null
+++ b/drivers/spi/bcm63xx_spi.c
-@@ -0,0 +1,479 @@
+@@ -0,0 +1,489 @@
+/*
+ * Broadcom BCM63xx SPI controller support
+ *
@@ -418,13 +418,13 @@
+ case 32:
+ clk_cfg = SPI_CLK_1_563MHZ;
+ break;
-+ case 128:
++ case 64:
+ clk_cfg = SPI_CLK_0_781MHZ;
+ break;
-+ case 64:
++ case 128:
+ default:
+ /* Set to slowest mode for compatibility */
-+ clk_cfg = SPI_CLK_0_781MHZ;
++ clk_cfg = SPI_CLK_0_391MHZ;
+ break;
+ }
+
@@ -527,6 +527,7 @@
+ /* Issue the transfer */
+ cmd = SPI_CMD_START_IMMEDIATE;
+ cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
++ cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
+ bcm_spi_writew(cmd, SPI_CMD);
+ wait_for_completion(&bs->done);
+
@@ -620,6 +621,7 @@
+ struct spi_master *master;
+ struct clk *clk;
+ struct bcm63xx_spi *bs;
++ uint32_t reg;
+ int ret;
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -699,6 +701,14 @@
+ goto out_reset_hw;
+ }
+
++ reg = bcm_gpio_readl(GPIO_MODE_REG);
++ reg |= GPIO_MODE_6358_EXTRA_SPI_SS;
++ bcm_gpio_writel(reg, GPIO_MODE_REG);
++
++ reg = bcm_gpio_readl(GPIO_CTL_HI_REG);
++ reg |= 0x3;
++ bcm_gpio_writel(reg, GPIO_CTL_HI_REG);
++
+ dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d) v%s\n",
+ r->start, irq, bs->fifo_size, DRV_VER);
+
@@ -982,7 +992,7 @@
#include <board_bcm963xx.h>
#define PFX "board_bcm963xx: "
-@@ -1596,6 +1597,9 @@ int __init board_register_devices(void)
+@@ -1602,6 +1603,9 @@ int __init board_register_devices(void)
if (board.num_spis)
spi_register_board_info(board.spis, board.num_spis);
--
1.7.3.2
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