. wrote:
So we guess the main question is, if we design an AES cryptocore(FPGA) how do we ensure that the cpu utilization will drop? This is more important than getting a higher throughput
the hardest part will be getting data in and out of your engine faster than the CPU can just process it itself. if the CPU has to spoonfeed your chip the data, it may well be SLOWER than using software.
remember, our CPUs now run at several-gigahertz speeds... most FPGA's start falling down around 100Mhz.
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