On Wed March 10 2010, . wrote: > Hello everybody. > > We are two students doing a project about accelerating encryption on an > embedded system. This system is build upon a ARM processor (180MHz) and an > FPGA. > We have built and implemented OpenSSH into the system (running Linux), and > tested the AES encryption in software. > The task is now to come up with a hardware component implemented on the FPGA > which will accelerate the encryption/decryption on the system. > We are trying to use the OpenSSL padlock as a reference and help. > Currently the ARM cpu usage is 100% when we transfer a file over OpenSSH > (SCP) in software encryption mode. > We are wondering if we implement an AES core on the FPGA and calls this core > from OpenSSL. What will happen with the CPU usage? > How can we tell if it will drop or not? > Where should we look in software? > > We have looked at the padlock.c file to get an overview of the > implementation of this engine, and tried to figure out if there is a > "special kind" of programming which > makes the cpu usage fall if using this engine. > > So we guess the main question is, if we design an AES cryptocore(FPGA) how > do we ensure that the cpu utilization will drop? This is more important than > getting a higher throughput > > PS. we are two electrical engineers so we are not that strong in software > development :-) >
The "padlock" engine uses the crypto instructions of the VIA processor - You can get the padlock documents from the VIA company site. Basicly, they are just extensions to the x86 "byte string" instructions; so management of the fpga thingy your working on should be the same as management of any long running, repeat string byte, sort of instruction. Mike > Hope to hear from you soon. > ______________________________________________________________________ OpenSSL Project http://www.openssl.org User Support Mailing List openssl-users@openssl.org Automated List Manager majord...@openssl.org
