Hello,
On 04.02.2011 01:38, Aaron Carroll wrote:
At a high level, I think it makes sense for functions to be explicit
about selecting an AP... I don't see any advantage to a "default".
I don't know if the AP always equal in a complete architecture or is this done at cpu vendor level.
For mem read/writes we need the AP with the CPU component. You can determine this by "dap info X"
command (as example cortex_r4/TMS570):
> dap info 0
AP ID register 0x14770001
Type is MEM-AP AHB
AP BASE 0xffffffff
No ROM table present
> dap info 1
AP ID register 0x04770002
Type is MEM-AP APB
AP BASE 0x80000000
ROM table in legacy format
MEMTYPE System memory not present. Dedicated debug bus.
> ROMTABLE[0x0] = 0x1003
> Component base address 0x80001000, start address 0x80001000
> Component class is 0x9, CoreSight component
> Type is 0x15, Debug Logic, Processor
> Peripheral ID[4..0] = hex 04 00 6b bc 14
> Part is -*- unrecognized -*-
ROMTABLE[0x4] = 0x2003
Component base address 0x80002000, start address 0x80002000
Component class is 0x9, CoreSight component
Type is 0x13, Trace Source, Processor
Peripheral ID[4..0] = hex 04 00 0b b9 30
Part is Cortex-R4 ETM (Embedded Trace)
ROMTABLE[0x8] = 0x3003
Component base address 0x80003000, start address 0x80003000
Component class is 0x9, CoreSight component
Type is 0x11, Trace Sink, Port
Peripheral ID[4..0] = hex 04 00 1b b9 12
Part is Coresight TPIU (Trace Port Interface Unit)
ROMTABLE[0xc] = 0x4003
Component base address 0x80004000, start address 0x80004000
Component class is 0x9, CoreSight component
Type is 0x04, Debug Control, other
Peripheral ID[4..0] = hex 00 00 09 70 00
Part is Cortex-M3 NVIC (Interrupt Controller)
ROMTABLE[0x10] = 0x0
End of ROM table
> dap info 2
AP ID register 0x14760010
Type is JTAG-AP
No ROM table present
> dap info 3
AP ID register 0x00000000
No AP found at this apsel 0x3
No ROM table present
If i look into the cortex_a8 sources then i think the cpu component is in AP 0 and there is no
switching needed. Can anyone send the "dap info X" output for a cortex_a8 ?
Is my assumption is true then the correct AP can select at a lower level and the higher level don't
need to know about the correct AP.
How this structure is looking in your multi core a9 ?
Regards,
Mathias
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