Great, keep us posted. Actually, this will definitely be generally
useful, because there are many other resources that can't be accessed
from the L3 interconnect: the MPCore private regions (per-core timers
and WDT), snoop-control unit, global interrupt controller, local PRCM,
and of course ROM. Any A9mp will have the same issue.
I wonder what the best way to is to implement this. One option could be
a table that maps address ranges to access methods. This would have to
be configured both cpu-cpu (e.g. Cortex-A9 per-core timers) and per-SoC
(e.g. OMAP4430 ROM). This would be almost totally transparent to the
user, but could be a configuration nightmare.
Otherwise it could be a flag to the various commands that specify the
access should be serviced by the cpu, rather than a direct access to the
host bus. Your thoughts?
I think we can start with the easy one ;-)
But at the moment I don't know which one is easier, maybe starting with
the "command flag option" will be the starting point ...I'll check
regards
Luca
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