On Mon, Aug 2, 2010 at 11:01 PM, David Brownell <davi...@pacbell.net> wrote: >> But why as low as 100kHz? > > Because no reset-init method is kicking > in the xtal oscillator and PLL, so the chip > is clocked almost as slow as it'll go.
OK. So 100kHz maximum JTAG khz is not a pathological sign? > You want faster? Write a real reset-init > method that clocks the chip faster ... at least > until app code kicks in and overrides. First priority is to establish that nothing is wrong as such at this point, faster comes later. I also need to know what jtag clock it is safe to run reset-init at.... -- Øyvind Harboe US toll free 1-866-980-3434 / International +47 51 63 25 00 http://www.zylin.com/zy1000.html ARM7 ARM9 ARM11 XScale Cortex JTAG debugger and flash programmer _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
