I have committed the attached config for the Avalue RSC-W910 sbc. http://www.avalue.com.tw/products/RSC-W910.cfm
Cheers Spen
>From 1619facb5ebce060c2cb35035e7801a8898a6296 Mon Sep 17 00:00:00 2001 From: Spencer Oliver <ntfr...@users.sourceforge.net> Date: Tue, 13 Jul 2010 14:17:00 +0100 Subject: [PATCH] cfg: add Avalue RSC-W910 config Signed-off-by: Spencer Oliver <ntfr...@users.sourceforge.net> --- tcl/board/rsc-w910.cfg | 62 ++++++++++++++++++++++++++++++++++++++++++++++++ tcl/target/nuc910.cfg | 27 +++++++++++++++++++++ 2 files changed, 89 insertions(+), 0 deletions(-) create mode 100644 tcl/board/rsc-w910.cfg create mode 100644 tcl/target/nuc910.cfg diff --git a/tcl/board/rsc-w910.cfg b/tcl/board/rsc-w910.cfg new file mode 100644 index 0000000..f7095a6 --- /dev/null +++ b/tcl/board/rsc-w910.cfg @@ -0,0 +1,62 @@ +# Avalue RSC-W8910 sbc +# http://www.avalue.com.tw/products/RSC-W910.cfm +# 2MB NOR Flash +# 64MB SDRAM +# 128MB NAND Flash + +# Based on Nuvoton nuc910 +source [find target/nuc910.cfg] + +# +# reset only behaves correctly if we use srst_pulls_trst +# +reset_config trst_and_srst srst_pulls_trst + +adapter_khz 1000 +adapter_nsrst_delay 100 +jtag_ntrst_delay 100 + +$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x04000000 -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME cfi 0x20000000 0x00200000 2 2 $_TARGETNAME + +# +# Target events +# + +$_TARGETNAME configure -event reset-start {adapter_khz 1000} + +$_TARGETNAME configure -event reset-init { + # switch on PLL for 200MHz operation + # running from 15MHz input clock + + mww 0xB0000200 0x45180bb1 # CLKEN + mww 0xB0000204 0x00000f3c # CLKSEL + mww 0xB0000208 0x05007000 # CLKDIV + mww 0xB000020C 0x00004f24 # PLLCON0 + mww 0xB0000210 0x00002b63 # PLLCON1 + sleep 10 + + # we are now running @ 200MHz + # enable all openocd speed tweaks + + arm7_9 dcc_downloads enable + arm7_9 fast_memory_access enable + adapter_khz 15000 + + # map nor flash to 0x20000000 + # map sdram to 0x00000000 + + mww 0xb0001000 0x000530c1 # EBICON + mww 0xb0001004 0x40030084 # ROMCON + mww 0xb0001008 0x000010ee # SDCONF0 + mww 0xb000100C 0x00000000 # SDCONF1 + mww 0xb0001010 0x0000015b # SDTIME0 + mww 0xb0001014 0x0000015b # SDTIME1 + mww 0xb0001018 0x00000000 # EXT0CON + mww 0xb000101C 0x00000000 # EXT1CON + mww 0xb0001020 0x00000000 # EXT2CON + mww 0xb0001024 0x00000000 # EXT3CON + mww 0xb000102c 0x00ff0048 # CKSKEW +} diff --git a/tcl/target/nuc910.cfg b/tcl/target/nuc910.cfg new file mode 100644 index 0000000..7fe91fe --- /dev/null +++ b/tcl/target/nuc910.cfg @@ -0,0 +1,27 @@ +# +# Nuvoton nuc910 (previously W90P910) based soc +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME nuc910 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # set useful default + set _CPUTAPID 0x07926f0f +} + +set _TARGETNAME $_CHIPNAME.cpu +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -- 1.7.1
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