Hi,
just finished my openocd.cfg for the Hitex LPC1768-Stick:
http://www.hitex.com/index.php?id=lpc1768-stick-details
It has an FT2232D for JTAG with "stm32stick" layout connected to
the NXP LPC1768 µC (Cortex M3).
The attached openocd.cfg contains the full configuration,
because the tcl/target/lpc1768.cfg seems to have some issues:
"arm core_state arm" is not possible on the LPC1768.
It also doesn't remap the Bootloader on Address 0x00000000
correctly. The LPC1768-Stick has only a 4 MHz
quartz crystal (needed for the flash definitio line).
A bigger issue was Reset configuration: OpenOCDs lpc1768.cfg
states: "trst_and_srst srst_pulls_trst" which seems to be correct,
BUT you cannot issue a "reset init" (unless you change the rest config
to "trst_only"). Why is there no fallback to "trst_only"...?
The reset_config "trst_and_srst separate" works for me too.
Thanks for a great jtag debugging tool,
-- J. Fischer
ps.
For Windows (7) 64 Bit Users: Hitex ships no 64 Bit drivers, and the
Tools won't install on 64 Bit Systems. But i could make FTDIs driver
work by adding the USB-IDs to the drivers inf files. My 32 Bit OpenOCD
linked to ftd2xx lib (using mingw gcc) works well on 64 Bit Windows 7 now.
#
# OpenOCD Configuration for Hitex LPC1768-Stick
#
#Interface: Hitex LPC1768-Stick
interface ft2232
ft2232_device_desc "LPC1768-Stick"
ft2232_layout stm32stick
ft2232_vid_pid 0x0640 0x0026
# MCU
# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
clocked with 4MHz internal RC oscillator
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME lpc1768
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x4ba00477
}
#delays on reset lines
jtag_nsrst_delay 200
jtag_ntrst_delay 200
# LPC2000 & LPC1700 -> SRST causes TRST
reset_config trst_and_srst separate
# reset_config trst_only srst_pulls_trst
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id
$_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position
$_TARGETNAME
# LPC1768 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000
-work-area-backup 0
$_TARGETNAME configure -event reset-init {
# Clock-Source internal IRC (~4MHz)
mwb 0x400FC10C 0x00
# Disable Bootloader
#do not remap 0x0000-0x0020 to anything but the flash
mwb 0x400FC040 0x01
}
# LPC1768 has 512kB of user-available FLASH (bootloader is located in separate
dedicated region).
# flash bank lpc1700 <base> <size> 0 0 <target#> <variant> <cclk>
[calc_checksum]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 4000
calc_checksum
# 4MHz / 6 = 666kHz, so use 500
jtag_khz 500
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