Update the DaVinci target configs so they have JTAG post-reset
event handlers which:
- run the 100 JTAG clocks ICEpick wants
- ensure the ARM (and ETB) taps are enabled
---
The OMAP3 post-reset handlers should probably do something
similar, doing the (updated) omap3_dbginit stuff so that it
no longer needs to be done by hand.
This patch needs a bit more sanity testing though; ideally
it will be updated so these boards no longer need to have
the EMU0/EMU1 jumpers in the non-default "enable ARM stuff
by default" setting. At which point they'll act mostly like
the OMAP3 stuff, except of course that (a) this generation
has ARM926 cores not Cortex-A8, and (b) SRST is available.
tcl/target/ti_dm355.cfg | 5 +++++
tcl/target/ti_dm365.cfg | 5 +++++
tcl/target/ti_dm6446.cfg | 7 +++++++
3 files changed, 17 insertions(+)
--- a/tcl/target/ti_dm355.cfg
+++ b/tcl/target/ti_dm355.cfg
@@ -44,6 +44,11 @@ if { [info exists JRC_TAPID ] } {
}
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id
$_JRC_TAPID
+# with normal EMU0/EMU1 settings, neither ARM nor ETB
+# are available after JTAG reset.
+jtag configure $_CHIPNAME.jrc -event post-reset \
+ "runtest 100; jtag tapenable $_CHIPNAME.arm; jtag tapenable
$_CHIPNAME.etb"
+
################
# various symbol definitions, to avoid hard-wiring addresses
--- a/tcl/target/ti_dm365.cfg
+++ b/tcl/target/ti_dm365.cfg
@@ -49,6 +49,11 @@ if { [info exists JRC_TAPID ] } {
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
-expected-id $_JRC_TAPID
+# with normal EMU0/EMU1 settings, neither ARM nor ETB
+# are available after JTAG reset.
+jtag configure $_CHIPNAME.jrc -event post-reset \
+ "runtest 100; jtag tapenable $_CHIPNAME.arm; jtag tapenable
$_CHIPNAME.etb"
+
################
# various symbol definitions, to avoid hard-wiring addresses
--- a/tcl/target/ti_dm6446.cfg
+++ b/tcl/target/ti_dm6446.cfg
@@ -60,6 +60,13 @@ if { [info exists JRC_TAPID ] } {
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
-expected-id $_JRC_TAPID
+# with normal EMU0/EMU1 settings, neither ARM nor ETB
+# are available after JTAG reset.
+jtag configure $_CHIPNAME.jrc -event post-reset \
+ "runtest 100; jtag tapenable $_CHIPNAME.arm; jtag tapenable
$_CHIPNAME.etb"
+
+################
+
# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K)
# and the ETB memory (4K) are other options, while trace is unused.
# Little-endian; use the OpenOCD default.
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