On Tuesday 04 August 2009, Andrew Rogers wrote: > > Any thoughts on how SWD should be done?
For those who don't know: SWD more or less takes part of the JTAG operational model and crams it into two wires. (I think some of the "more" involves ability to send some messages, like trace data, asynchronously. Maybe someone can provide a good summary? Or a link to one...) Newer ARMs can support it as an option (Cortex-M3, etc). The chips tend to start in JTAG mode, you send a magic set of state machine transitions, now it's in SWD. Send a different set of transitions, it's back in JTAG mode. There's a *different* two-wire model in IEEE 1149.7 ... and a third in Nexus, ISTR. I would want to see the stack, at some level, branch so that any of those four models can be used beneath the current scripting calls. That may require some re-layering. If one layer can be "TAP", accessing TAPs through JTAG should work ... or depending on the chip, one of the other three schemes (SWD being one). There would need to be a command to force one of those modes. FT2232 interfaces can for example support both JTAG and SWD. What does that mean at the driver level? - Dave _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
