I have a very simple code which just blinks the LED. The code itself is
fine.
When I upload the code and just run it everything is fine. When I try to
debug the same code that I've uploaded before (flash is not modified)
some registers have some funny values which make the code work wrong.
When I close OpenOCD and reset the chip again everything works fine...
WTF?
I've done some investigation and everything is even stranger...
I use GDB Hardware Debugging plugin in Eclipse. I put a breakpoint at main.
When the core hits the breakpoint I inspect the registers:
> reg
(11) r11 (/32): 0x400001F9 (dirty: 0, valid: 1)
(13) r13_usr (/32): 0x400001EC (dirty: 0, valid: 1)
R11 and SP are the register that miraculously have such strange values,
because before main there are just three lines that modify them:
0x000000e8 <main>: push {r11, lr}
0x000000ec <main+4>: add r11, sp, #4 ; 0x4
0x000000f0 <main+8>: sub sp, sp, #8 ; 0x8
(the SP is setup in the startup of course, the value for that is
0x40000200. That's pretty easy to count that R11 should be 0x400001FC
and SP should be ...1F0.
Now the funny part... When I put my first breakpoint at Reset_Handler
(that's exactly what you think), and then put breakpoint at the first
line that modifies R11 (the first one of the three above) everything
works... The reg dump at the same point as before (3 lines further, at
the beginning of main):
(11) r11 (/32): 0x400001FC (dirty: 0, valid: 1)
(13) r13_usr (/32): 0x400001F0 (dirty: 0, valid: 1)
When I reset and stop at Reset_Handler, then run to main directly
without that breakpoint in-the-middle - the reg values are wrong /;
I've tried OpenOCD-r2498, 0.1.0 and some revs in between - the same
I've tried GDB from the most recent CodeSourcery and from some older
version of Yagarto - the same.
When I close OpenOCD and reset the chip the code works fine. During the
whole process the contents of flash were exactly the same...
Any ideas? Any help? Who should I blame?
Thx in advance...
4\/3!!
full register dump at the beginning of main (only R11 and SP are
different...):
WRONG:
(0) r0 (/32): 0x000000E8 (dirty: 1, valid: 1)
(1) r1 (/32): 0x40000000 (dirty: 1, valid: 1)
(2) r2 (/32): 0x40000000 (dirty: 0, valid: 1)
(3) r3 (/32): 0x40000000 (dirty: 0, valid: 1)
(4) r4 (/32): 0xFFFFFFFF (dirty: 0, valid: 1)
(5) r5 (/32): 0xFFFFFFFF (dirty: 0, valid: 1)
(6) r6 (/32): 0xFFFFFFFF (dirty: 0, valid: 1)
(7) r7 (/32): 0xFFFFFFFF (dirty: 0, valid: 1)
(8) r8 (/32): 0xFFFFFFFF (dirty: 0, valid: 1)
(9) r9 (/32): 0xFFFFFFFF (dirty: 0, valid: 1)
(10) r10 (/32): 0xFFFFFFFF (dirty: 0, valid: 1)
(11) r11 (/32): 0x400001F5 (dirty: 0, valid: 1)
(12) r12 (/32): 0xFFFFFFFF (dirty: 0, valid: 1)
(13) r13_usr (/32): 0x400001E8 (dirty: 0, valid: 1)
(14) lr_usr (/32): 0x000000B0 (dirty: 0, valid: 1)
(15) pc (/32): 0x000000F4 (dirty: 1, valid: 1)
(16) r8_fiq (/32): 0x00000000 (dirty: 0, valid: 0)
(17) r9_fiq (/32): 0x00000000 (dirty: 0, valid: 0)
(18) r10_fiq (/32): 0x00000000 (dirty: 0, valid: 0)
(19) r11_fiq (/32): 0x00000000 (dirty: 0, valid: 0)
(20) r12_fiq (/32): 0x00000000 (dirty: 0, valid: 0)
(21) r13_fiq (/32): 0x00000000 (dirty: 0, valid: 0)
(22) lr_fiq (/32): 0x00000000 (dirty: 0, valid: 0)
(23) r13_irq (/32): 0x00000000 (dirty: 0, valid: 0)
(24) lr_irq (/32): 0x00000000 (dirty: 0, valid: 0)
(25) r13_svc (/32): 0x40000200 (dirty: 0, valid: 0)
(26) lr_svc (/32): 0x7FFFE35F (dirty: 0, valid: 0)
(27) r13_abt (/32): 0x00000000 (dirty: 0, valid: 0)
(28) lr_abt (/32): 0x00000000 (dirty: 0, valid: 0)
(29) r13_und (/32): 0x00000000 (dirty: 0, valid: 0)
(30) lr_und (/32): 0x00000000 (dirty: 0, valid: 0)
(31) cpsr (/32): 0x60000010 (dirty: 0, valid: 1)
(32) spsr_fiq (/32): 0x00000000 (dirty: 0, valid: 0)
(33) spsr_irq (/32): 0x00000000 (dirty: 0, valid: 0)
(34) spsr_svc (/32): 0x00000010 (dirty: 0, valid: 0)
(35) spsr_abt (/32): 0x00000000 (dirty: 0, valid: 0)
(36) spsr_und (/32): 0x00000000 (dirty: 0, valid: 0)
(37) debug_ctrl (/6): 0x05 (dirty: 0, valid: 1)
(38) debug_status (/5): 0x09 (dirty: 0, valid: 0)
(39) comms_ctrl (/32): 0x40000000 (dirty: 0, valid: 0)
(40) comms_data (/32): 0x00000000 (dirty: 0, valid: 0)
(41) watch 0 addr value (/32): 0x000000F4 (dirty: 0, valid: 1)
(42) watch 0 addr mask (/32): 0x00000003 (dirty: 0, valid: 1)
(43) watch 0 data value (/32): 0x00000000 (dirty: 0, valid: 0)
(44) watch 0 data mask (/32): 0xFFFFFFFF (dirty: 0, valid: 1)
(45) watch 0 control value (/32): 0x00000000 (dirty: 0, valid: 1)
(46) watch 0 control mask (/32): 0x000000F7 (dirty: 0, valid: 1)
(47) watch 1 addr value (/32): 0x000000F4 (dirty: 0, valid: 1)
(48) watch 1 addr mask (/32): 0x00000003 (dirty: 0, valid: 1)
(49) watch 1 data value (/32): 0x00000000 (dirty: 0, valid: 0)
(50) watch 1 data mask (/32): 0xFFFFFFFF (dirty: 0, valid: 1)
(51) watch 1 control value (/32): 0x00000000 (dirty: 0, valid: 1)
(52) watch 1 control mask (/32): 0x000000F7 (dirty: 0, valid: 1)
RIGHT:
(0) r0 (/32): 0x000000E8 (dirty: 1, valid: 1)
(1) r1 (/32): 0x40000000 (dirty: 1, valid: 1)
(2) r2 (/32): 0x40000000 (dirty: 0, valid: 1)
(3) r3 (/32): 0x40000000 (dirty: 0, valid: 1)
(4) r4 (/32): 0xFFFFFFFF (dirty: 0, valid: 1)
(5) r5 (/32): 0xFFFFFFFF (dirty: 0, valid: 1)
(6) r6 (/32): 0xFFFFFFFF (dirty: 0, valid: 1)
(7) r7 (/32): 0xFFFFFFFF (dirty: 0, valid: 1)
(8) r8 (/32): 0xFFFFFFFF (dirty: 0, valid: 1)
(9) r9 (/32): 0xFFFFFFFF (dirty: 0, valid: 1)
(10) r10 (/32): 0xFFFFFFFF (dirty: 0, valid: 1)
(11) r11 (/32): 0x400001FC (dirty: 0, valid: 1)
(12) r12 (/32): 0xFFFFFFFF (dirty: 0, valid: 1)
(13) r13_usr (/32): 0x400001F0 (dirty: 0, valid: 1)
(14) lr_usr (/32): 0x000000B0 (dirty: 0, valid: 1)
(15) pc (/32): 0x000000F4 (dirty: 1, valid: 1)
(16) r8_fiq (/32): 0x00000000 (dirty: 0, valid: 0)
(17) r9_fiq (/32): 0x00000000 (dirty: 0, valid: 0)
(18) r10_fiq (/32): 0x00000000 (dirty: 0, valid: 0)
(19) r11_fiq (/32): 0x00000000 (dirty: 0, valid: 0)
(20) r12_fiq (/32): 0x00000000 (dirty: 0, valid: 0)
(21) r13_fiq (/32): 0x00000000 (dirty: 0, valid: 0)
(22) lr_fiq (/32): 0x00000000 (dirty: 0, valid: 0)
(23) r13_irq (/32): 0x00000000 (dirty: 0, valid: 0)
(24) lr_irq (/32): 0x00000000 (dirty: 0, valid: 0)
(25) r13_svc (/32): 0x40000200 (dirty: 0, valid: 0)
(26) lr_svc (/32): 0x7FFFE35F (dirty: 0, valid: 0)
(27) r13_abt (/32): 0x00000000 (dirty: 0, valid: 0)
(28) lr_abt (/32): 0x00000000 (dirty: 0, valid: 0)
(29) r13_und (/32): 0x00000000 (dirty: 0, valid: 0)
(30) lr_und (/32): 0x00000000 (dirty: 0, valid: 0)
(31) cpsr (/32): 0x60000010 (dirty: 0, valid: 1)
(32) spsr_fiq (/32): 0x00000000 (dirty: 0, valid: 0)
(33) spsr_irq (/32): 0x00000000 (dirty: 0, valid: 0)
(34) spsr_svc (/32): 0x00000010 (dirty: 0, valid: 0)
(35) spsr_abt (/32): 0x00000000 (dirty: 0, valid: 0)
(36) spsr_und (/32): 0x00000000 (dirty: 0, valid: 0)
(37) debug_ctrl (/6): 0x05 (dirty: 0, valid: 1)
(38) debug_status (/5): 0x09 (dirty: 0, valid: 0)
(39) comms_ctrl (/32): 0x40000000 (dirty: 0, valid: 0)
(40) comms_data (/32): 0x00000000 (dirty: 0, valid: 0)
(41) watch 0 addr value (/32): 0x000000E8 (dirty: 0, valid: 1)
(42) watch 0 addr mask (/32): 0x00000003 (dirty: 0, valid: 1)
(43) watch 0 data value (/32): 0x00000000 (dirty: 0, valid: 0)
(44) watch 0 data mask (/32): 0xFFFFFFFF (dirty: 0, valid: 1)
(45) watch 0 control value (/32): 0x00000000 (dirty: 0, valid: 1)
(46) watch 0 control mask (/32): 0x000000F7 (dirty: 0, valid: 1)
(47) watch 1 addr value (/32): 0x000000F4 (dirty: 0, valid: 1)
(48) watch 1 addr mask (/32): 0x00000003 (dirty: 0, valid: 1)
(49) watch 1 data value (/32): 0x00000000 (dirty: 0, valid: 0)
(50) watch 1 data mask (/32): 0xFFFFFFFF (dirty: 0, valid: 1)
(51) watch 1 control value (/32): 0x00000000 (dirty: 0, valid: 1)
(52) watch 1 control mask (/32): 0x000000F7 (dirty: 0, valid: 1)
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