Magnus Lundin wrote:
> Now compare the reported start addresses below with table 5-105 in
> OMAP35x TRM, SPRUF98B–September 2008,
> and table 2-3 in CoreSight Components, and the management registers in
>
>>> dap info 1
>> ap identification register 0x04770002
>> Type is mem-ap APB
>> ap debugbase 0x80000000
>> ROM table in legacy format
>> CID3 0xb1, CID2 0x5, CID1 0x10, CID0, 0xd
>> MEMTYPE system memory not present. Dedicated debug bus
>> ROMTABLE[0x0] = 0xd4010003
>> Component base address 0x54010000, pid4 0x4, start address 0x54010000
> MPU SS Module
>> Component cid1 0x90, class is CoreSight component
>> CID3 0xb1, CID2 0x5, CID1 0x90, CID0, 0xd
>> PID3 0x10, PID2 0x2b, PID1 0xb9, PID0, 0x21
> Part number from PID1 and PID 0 is 0x921
>> ROMTABLE[0x4] = 0xd4011003
>> Component base address 0x54011000, pid4 0x4, start address 0x54011000
> This is the Debug Reister Interface, se part number below and table 12-3
> in the Cortex-A8 TRM
...
> So obviously we are getting meaningful results back from the DAP. Next
> step is to try to talk to the specific module registers.
Trying to access Debug Reister Interface with mdw I get
> omap3.cpu mdw 0x54011000
0x54011000 15141012
Looking at Cortex-A8 TRM, it seems to me that this is Debug ID
register (table 12-11):
[31-28] WRP: 0x1 -> 2 WRPs are implemented
[27-24] BRP: 0x5 -> 6 BRPs are implemented
[23-20] Context: 0x1 -> 2 BRPs have context ID capability
[19-16] Debug architecture version: 0x4 -> ARMv7 debug
[12] security: 0x0 -> no security extension
[7-4] variant: 0x1
[3-0] revision: 0x2
Seems that it is correct what we read here :)
Best regards
Dirk
Btw. #1: I'm from time to time at #openjtag. Sometimes IRC is good for
faster discussion ;)
Btw. #2: I still have issues with mdw [COUNT] parameter:
> omap3.cpu mdw 0x54011000 16
Runtime error, file "command.c", line 456:
expected: mdw ADDR [COUNT]
Any idea?
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