Now compare the reported start addresses below with table 5-105 in OMAP35x TRM, SPRUF98B–September 2008, and table 2-3 in CoreSight Components, and the management registers in
> > dap info 1 > ap identification register 0x04770002 > Type is mem-ap APB > ap debugbase 0x80000000 > ROM table in legacy format > CID3 0xb1, CID2 0x5, CID1 0x10, CID0, 0xd > MEMTYPE system memory not present. Dedicated debug bus > ROMTABLE[0x0] = 0xd4010003 > Component base address 0x54010000, pid4 0x4, start address 0x54010000 MPU SS Module > Component cid1 0x90, class is CoreSight component > CID3 0xb1, CID2 0x5, CID1 0x90, CID0, 0xd > PID3 0x10, PID2 0x2b, PID1 0xb9, PID0, 0x21 Part number from PID1 and PID 0 is 0x921 > > ROMTABLE[0x4] = 0xd4011003 > Component base address 0x54011000, pid4 0x4, start address 0x54011000 This is the Debug Reister Interface, se part number below and table 12-3 in the Cortex-A8 TRM > Component cid1 0x90, class is CoreSight component > CID3 0xb1, CID2 0x5, CID1 0x90, CID0, 0xd > PID3 0x10, PID2 0x2b, PID1 0xbc, PID0, 0x8 Part number 0xc08 > > ROMTABLE[0x8] = 0xd4012003 > Component base address 0x54012000, pid4 0x0, start address 0x54012000 ???? > Component cid1 0x90, class is CoreSight component > CID3 0xb1, CID2 0x5, CID1 0x90, CID0, 0xd > PID3 0x0, PID2 0x9, PID1 0x71, PID0, 0x13 > ROMTABLE[0xc] = 0xd4013002 > Component not present > ROMTABLE[0x10] = 0xd4019003 > Component base address 0x54019000, pid4 0x4, start address 0x54019000 TPIU Module > Component cid1 0x90, class is CoreSight component > CID3 0xb1, CID2 0x5, CID1 0x90, CID0, 0xd > PID3 0x0, PID2 0x1b, PID1 0xb9, PID0, 0x12 Part number 0x912 > ROMTABLE[0x14] = 0xd401b003 > Component base address 0x5401b000, pid4 0x4, start address 0x5401b000 ETB Module > Component cid1 0x90, class is CoreSight component > CID3 0xb1, CID2 0x5, CID1 0x90, CID0, 0xd > PID3 0x0, PID2 0xb, PID1 0xb9, PID0, 0x7 > ROMTABLE[0x18] = 0xd401d003 > Component base address 0x5401d000, pid4 0x0, start address 0x5401d000 DAP CTL Module > Component cid1 0xf0, class is Non standard layout > CID3 0xb1, CID2 0x5, CID1 0xf0, CID0, 0xd > PID3 0x0, PID2 0x9, PID1 0x73, PID0, 0x43 > ROMTABLE[0x1c] = 0xd4500003 > Component base address 0x54500000, pid4 0x0, start address 0x54500000 SDTI Module > Component cid1 0x90, class is CoreSight component > CID3 0xb1, CID2 0x5, CID1 0x90, CID0, 0xd > PID3 0x0, PID2 0x19, PID1 0x71, PID0, 0x20 > ROMTABLE[0x20] = 0x0 > End of ROM table > So obviously we are getting meaningful results back from the DAP. Next step is to try to talk to the specific module registers. Regards, Magnus _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
