---
src/target/board/sheevaplug.cfg | 111 +++++++++++++++++++++++++++++++++++++++
1 files changed, 111 insertions(+), 0 deletions(-)
create mode 100644 src/target/board/sheevaplug.cfg
diff --git a/src/target/board/sheevaplug.cfg b/src/target/board/sheevaplug.cfg
new file mode 100644
index 0000000..e9c6832
--- /dev/null
+++ b/src/target/board/sheevaplug.cfg
@@ -0,0 +1,111 @@
+# Marvell SheevaPlug
+
+source [find interface/sheevaplug.cfg]
+source [find target/feroceon.cfg]
+
+$_TARGETNAME configure -event reset-init { sheevaplug_init }
+
+$_TARGETNAME configure \
+ -work-area-phys 0x10000000 \
+ -work-area-size 65536 \
+ -work-area-backup 0
+
+arm7_9 dcc_downloads enable
+
+# this assumes the hardware default peripherals location before u-Boot moves it
+nand device orion 0 0xd8000000
+
+proc sheevaplug_init { } {
+
+ arm926ejs cp15 0 0 1 0 0x00052078
+
+ mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
+ mww 0xD0001404 0x39543000 # Dunit Control Low Register
+ mww 0xD0001408 0x22125451 # DDR SDRAM Timing (Low) Register
+ mww 0xD000140C 0x00000833 # DDR SDRAM Timing (High) Register
+ mww 0xD0001410 0x000000CC # DDR SDRAM Address Control Register
+ mww 0xD0001414 0x00000000 # DDR SDRAM Open Pages Control Register
+ mww 0xD0001418 0x00000000 # DDR SDRAM Operation Register
+ mww 0xD000141C 0x00000C52 # DDR SDRAM Mode Register
+ mww 0xD0001420 0x00000042 # DDR SDRAM Extended Mode Register
+ mww 0xD0001424 0x0000F17F # Dunit Control High Register
+ mww 0xD0001428 0x00085520 # Dunit Control High Register
+ mww 0xD000147c 0x00008552 # Dunit Control High Register
+ mww 0xD0001504 0x0FFFFFF1 # CS0n Size Register
+ mww 0xD0001508 0x10000000 # CS1n Base Register
+ mww 0xD000150C 0x0FFFFFF5 # CS1n Size Register
+ mww 0xD0001514 0x00000000 # CS2n Size Register
+ mww 0xD000151C 0x00000000 # CS3n Size Register
+ mww 0xD0001494 0x003C0000 # DDR2 SDRAM ODT Control (Low) Register
+ mww 0xD0001498 0x00000000 # DDR2 SDRAM ODT Control (High) REgister
+ mww 0xD000149C 0x0000F80F # DDR2 Dunit ODT Control Register
+ mww 0xD0001480 0x00000001 # DDR SDRAM Initialization Control Register
+ mww 0xD0020204 0x00000000 # Main IRQ Interrupt Mask Register
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+
+ mww 0xD0010000 0x01111111 # MPP 0 to 7
+ mww 0xD0010004 0x11113322 # MPP 8 to 15
+ mww 0xD0010008 0x00001111 # MPP 16 to 23
+
+ mww 0xD0010418 0x003E07CF # NAND Read Parameters REgister
+ mww 0xD001041C 0x000F0F0F # NAND Write Parameters Register
+ mww 0xD0010470 0x01C7D943 # NAND Flash Control Register
+
+}
+
+proc sheevaplug_reflash_uboot { } {
+
+ # reflash the u-Boot binary
+ #reset init
+ nand probe 0
+ nand erase 0 0 4
+ nand write 0 uboot.bin 0
+ reset run
+
+}
+
+proc sheevaplug_load_uboot { } {
+
+ # load u-Boot into RAM
+ #reset init
+ load_image /tmp/uboot.elf
+ verify_image uboot.elf
+ resume 0x00600000
+
+}
+
--
1.6.2-rc2.GIT
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