This is an automated email from Gerrit. "Name of user not set <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9518
-- gerrit commit 4f7ab3855451ffdbaf0d193fff6d29548c11109b Author: Frederic Boyer <[email protected]> Date: Thu Apr 9 15:08:57 2026 +0200 tcl/board: add Microchip SAMA7G54-EK board configuration Add board configuration for the SAMA7G54-EK evaluation kit. Link: https://www.microchip.com/en-us/development-tool/EV21H18A Change-Id: I96f3706a76c7322db752b053c9071ed9fa1fc07f Signed-off-by: Frederic Boyer <[email protected]> diff --git a/tcl/board/microchip/sama7g54_ek.cfg b/tcl/board/microchip/sama7g54_ek.cfg new file mode 100644 index 0000000000..0f0e9ddd22 --- /dev/null +++ b/tcl/board/microchip/sama7g54_ek.cfg @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Board configuration for Microchip SAMA7G54-EK evaluation kit +# https://www.microchip.com/en-us/development-tool/EV21H18A +# Datasheet: DS60001765 +# User Guide: DS50003273 +# +# Debug Interface Selection: +# The SAMA7G54-EK has TWO debug paths controlled by jumper J26: +# +# J26 OPEN (factory default): +# - On-board J-Link-OB (ATSAM3U4C) is ENABLED +# - Connect via USB port J24 +# - Provides JTAG + CDC serial (virtual COM port) +# +# J26 CLOSED (this board file's default configuration): +# - On-board J-Link-OB is DISABLED +# - External JTAG/SWD probe connects to 20-pin header J27 +# +# IMPORTANT: J27 is only active when J26 is CLOSED. +# Using J27 with J26 open will NOT work. +# +# IMPORTANT: +# First-time JTAG Connection on blank board (no AT91Bootstrap in NVM): +# 1. Power on the board via J7 (USB Micro-AB) or J1 (DC jack) +# 2. ROM code searches for valid boot media +# 3. No valid code found -> ROM enters SAM-BA Monitor +# 4. SAM-BA Monitor enables JTAG -- OpenOCD can now connect +# To force SAM-BA entry on a board with programmed NVM: +# - Press and hold SW4 (DISABLE_BOOT) during power-on, OR +# - Close jumper J22 to permanently disable on-board boot memories +# - LED D8 RED = boot memories disabled, GREEN = enabled +# - Note: SW4/J22 does NOT disable SD Card boot -- remove card from J4 +# +# Typical Boot sequence (when debugging via JTAG/SWD): +# 1. Load AT91Bootstrap to SRAM (0x00100000) +# - Initializes clocks, DDR, peripherals, disables watchdog +# 2. Load application to DDR (0x60000000) +# - Zephyr, Linux, or bare-metal application +# - DDR must be initialized by AT91Bootstrap first +# +# Reset sources on this board: +# - Power-on reset from MCP16502 PMIC +# - User push button SW2 (Board Reset, connected to NRST) +# - External JTAG/J-Link-OB reset from debug probe +# +# Usage with external probe on J27 (J26 MUST be closed): +# openocd -f interface/jlink.cfg -f board/microchip/sama7g54_ek.cfg +# +# Usage with SWD (external probe): +# openocd -f interface/jlink.cfg -c "transport select swd" \ +# -f board/microchip/sama7g54_ek.cfg + +# Default to JTAG -- silently ignored if already selected +catch { transport select jtag } + +# Target configuration (supports both JTAG and SWD) +source [find target/microchip/sama7g5.cfg] + +# Board-specific adapter speed +# Start at lower speed for reliable initial connection. +# Speed increases to 4 MHz after reset-init event (configured in target file). +adapter speed 1000 + +# Reset configuration for external probe on J27 (J26 closed). +# Both SRST (pin 15/nRST) and TRST (pin 3/NTRST) are available +# on the 20-pin JTAG header. +# NTRST (PC25) has an internal pull-up -- safe to connect. +# +# srst_nogate: SRST is not gated by the JTAG state machine -- +# required because NRST resets the entire chip including debug logic. +# +# For probes with only SRST wired (no TRST), use instead: +# reset_config srst_only srst_nogate +# +reset_config trst_and_srst srst_nogate --
