This is an automated email from Gerrit. "Name of user not set <[email protected]>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/9519
-- gerrit commit d969ea90abe7693373e8c84c3139fcd555408333 Author: Frederic Boyer <[email protected]> Date: Thu Apr 9 15:09:41 2026 +0200 tcl/target: add SAMA7D6 target configuration Add target configuration for the Microchip SAMA7D6 series (Cortex-A7 based MPU). Supports both JTAG and SWD interfaces. Work area configured in SRAM for NVM programming and memory operations. Link: https://www.microchip.com/en-us/product/sama7d65 Change-Id: I2568c9cf3f6a5ae809055669a97ba5c63ee491eb Signed-off-by: Frederic Boyer <[email protected]> diff --git a/tcl/target/microchip/sama7d6.cfg b/tcl/target/microchip/sama7d6.cfg new file mode 100644 index 0000000000..650a6e01a1 --- /dev/null +++ b/tcl/target/microchip/sama7d6.cfg @@ -0,0 +1,175 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Target configuration for Microchip SAMA7D6 series +# +# Cortex-A7 based Microprocessor Unit (MPU) +# https://www.microchip.com/en-us/product/sama7d65 +# Datasheet: DS60001851 +# +# SAMA7D6 series currently includes: +# - SAMA7D65 +# +# Supports both JTAG and SWD transports. +# Select transport before sourcing this file: +# -c "transport select jtag" +# -c "transport select swd" +# If not specified, the adapter driver will auto-select. +# +# IMPORTANT: JTAG/SWD Access Requires ROM Code Completion +# The SAMA7D65 ROM code disables JTAG during boot. +# JTAG is enabled only after one of: +# a) The ROM code finds a valid boot image (e.g., AT91Bootstrap) +# and jumps to SRAM -- JTAG is enabled at that point +# b) No valid NVM found -- ROM code enters SAM-BA Monitor, +# enables USB + UART + JTAG connection +# +# On a blank/fresh board with no NVM programmed: +# - Power on the board +# - Wait for ROM code to enter SAM-BA Monitor +# - JTAG is then enabled automatically +# +# JTAG/Debug Security (OTP Fuses): +# OTPC_UHC0R.JTAGDIS[7:0] = 0x00 (default): JTAG enabled +# OTPC_UHC0R.JTAGDIS[7:0] != 0x00: JTAG permanently disabled +# OTPC_UHC0R.SECDBG[7:0] = 0x00 (default): Secure debug allowed +# OTPC_UHC0R.SECDBG[7:0] != 0x00: Secure debug permanently forbidden +# WARNING: If these OTP fuses are blown, JTAG/SWD is permanently disabled. +# +# Hardware watchdog warning: +# When connecting before AT91Bootstrap runs, the hardware watchdog +# may reset the chip periodically, causing transient DAP errors. +# OpenOCD automatically recovers by re-examining the target. +# The watchdog is disabled by AT91Bootstrap during normal boot. +# + +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME sama7d6 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # ARM CoreSight JTAG-DP IDCODE + # Version=0x6, Part=0xBA00, Designer=ARM Ltd. + set _CPUTAPID 0x6ba00477 +} + +if { [info exists DAP_TAPID] } { + set _DAP_TAPID $DAP_TAPID +} else { + # ARM CoreSight SW-DP DPIDR + set _DAP_TAPID 0x6ba02477 +} + +# +# JTAG or SWD configuration +# +if { [using_jtag] } { + jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID +} else { + swd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID +} + +# +# DAP (Debug Access Port) -- required for Cortex-A targets +# +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +# +# Target: Cortex-A7 (single core) +# +set _TARGETNAME $_CHIPNAME.cpu.0 +target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -endian $_ENDIAN -coreid 0 + +# +# SRAM: 128KB at 0x00100000 +# Used by OpenOCD as work area for flash programming and memory operations. +# +# CAUTION: This SRAM is shared with the ROM code and AT91Bootstrap. +# - During boot: ROM code uses SRAM for bootloader operations +# - After AT91Bootstrap: SRAM contains bootstrap code +# - Set -work-area-backup 1 if you need to preserve SRAM contents +# +$_TARGETNAME configure -work-area-phys 0x00100000 -work-area-size 0x20000 -work-area-backup 0 + +# +# Event handlers +# + +$_TARGETNAME configure -event examine-start { + # Start at conservative speed for reliable initial connection. + adapter speed 1000 +} + +$_TARGETNAME configure -event examine-end { + # Halt CPU immediately to prevent WFI sleep mode + # which can power down debug regions. + # + # Note: This will fail if the ROM code has not yet enabled JTAG. + # JTAG is disabled during ROM code execution and only enabled after: + # - A valid boot image is found and execution jumps to SRAM, OR + # - The SAM-BA Monitor is entered (no valid NVM found) + # Transient errors here are expected and recoverable. + if { [catch { $_TARGETNAME arp_halt }] } { + echo "Warning: Could not halt target." + echo " JTAG may not be enabled yet (ROM code disables it during boot)." + echo " Ensure AT91Bootstrap is flashed, or wait for SAM-BA Monitor entry." + } + catch { $_TARGETNAME arp_waitstate halted 1000 } +} + +$_TARGETNAME configure -event gdb-attach { + # Halt CPU when debugger connects + halt +} + +$_TARGETNAME configure -event gdb-detach { + # Resume CPU when debugger disconnects + resume +} + +$_TARGETNAME configure -event reset-start { + # Reduce speed during reset for stability + adapter speed 1000 +} + +$_TARGETNAME configure -event reset-init { + # Increase speed after reset initialization + adapter speed 4000 +} + +# +# Troubleshooting: +# +# Connection fails immediately after power-on: +# - JTAG is disabled by ROM code during boot +# - On a blank board, wait for SAM-BA Monitor to enable JTAG +# - If AT91Bootstrap is flashed in NVM, JTAG is enabled at SRAM jump +# +# Connection permanently fails: +# - Check OTPC_UHC0R.JTAGDIS fuse -- if non-zero, JTAG is permanently disabled +# - Check OTPC_UHC0R.SECDBG fuse -- if non-zero, secure debug is forbidden +# +# Hardware checks: +# - Ensure JTAGSEL pin is LOW (default with internal pull-down) +# - Ensure TST pin is LOW (must be tied low for normal operation) +# - NTRST (PC22) has internal pull-up (deasserted by default) +# - Verify VDDIN33 power is stable (powers all debug pins PC22-PC26) +# - Use lower adapter speeds (1000 kHz) if experiencing intermittent errors +# - Watchdog resets are normal before AT91Bootstrap disables it +# +# SAM-BA Monitor recovery (when no valid NVM boot image exists): +# - ROM code enters SAM-BA Monitor automatically, enabling JTAG +# - Serial console available at 115200 baud, 8N1 +# - See board configuration file for board-specific USB and UART details +# --
