On 12.02.2021 19:00, Shyam Sundar S K wrote: > Frequent link up/down events can happen when a Bel Fuse SFP part is > connected to the amd-xgbe device. Try to avoid the frequent link > issues by resetting the PHY as documented in Bel Fuse SFP datasheets. > > Signed-off-by: Sudheesh Mavila <sudheesh.mav...@amd.com> > Signed-off-by: Shyam Sundar S K <shyam-sundar....@amd.com> > --- > drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c > b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c > index 1bb468ac9635..e328fd9bd294 100644 > --- a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c > +++ b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c > @@ -922,6 +922,12 @@ static bool xgbe_phy_belfuse_phy_quirks(struct > xgbe_prv_data *pdata) > if ((phy_id & 0xfffffff0) != 0x03625d10) > return false; > > + /* Reset PHY - wait for self-clearing reset bit to clear */ > + reg = phy_read(phy_data->phydev, 0x00); > + phy_write(phy_data->phydev, 0x00, reg | 0x8000); > + read_poll_timeout(phy_read, reg, !(reg & 0x8000) || reg < 0, > + 10000, 50000, true, phy_data->phydev, 0x0); > +
Why don't you simply use genphy_soft_reset() ? Also it's not too nice to use magic register and bit numbers, there are constants available, e.g. 0x00 = MII_BMCR > /* Disable RGMII mode */ > phy_write(phy_data->phydev, 0x18, 0x7007); > reg = phy_read(phy_data->phydev, 0x18); >
