On Mon, Dec 14, 2020 at 1:49 PM Saeed Mahameed <sa...@kernel.org> wrote:
>
> From: Parav Pandit <pa...@nvidia.com>
>
> MLX5_GENERAL_OBJECT_TYPES types bitfield is 64-bit field.
>
> Defining an enum for such bit fields on 32-bit platform results in below
> warning.
>
> ./include/vdso/bits.h:7:26: warning: left shift count >= width of type
> [-Wshift-count-overflow]
> ^
> ./include/linux/mlx5/mlx5_ifc.h:10716:46: note: in expansion of macro ‘BIT’
> MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT(0x20),
> ^~~
> Use 32-bit friendly left shift.
>
> Fixes: 2a2970891647 ("net/mlx5: Add sample offload hardware bits and
> structures")
> Signed-off-by: Parav Pandit <pa...@nvidia.com>
> Reported-by: Stephen Rothwell <s...@canb.auug.org.au>
> Signed-off-by: Leon Romanovsky <leo...@nvidia.com>
> Signed-off-by: Saeed Mahameed <sa...@kernel.org>
> ---
> include/linux/mlx5/mlx5_ifc.h | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
> index 0d6e287d614f..b9f15935dfe5 100644
> --- a/include/linux/mlx5/mlx5_ifc.h
> +++ b/include/linux/mlx5/mlx5_ifc.h
> @@ -10711,9 +10711,9 @@ struct mlx5_ifc_affiliated_event_header_bits {
> };
>
> enum {
> - MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
> - MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT(0x13),
> - MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT(0x20),
> + MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 1ULL << 0xc,
> + MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = 1ULL << 0x13,
> + MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = 1ULL << 0x20,
> };
Why not just use BIT_ULL?
