On Thu, Sep 03, 2020 at 11:36:39PM +0200, Marek Vasut wrote: > On 9/3/20 11:00 PM, Andrew Lunn wrote: > > On Thu, Sep 03, 2020 at 10:27:12PM +0200, Marek Vasut wrote: > >> The phy_reset_after_clk_enable() does a PHY reset, which means the PHY > >> loses its register settings. The fec_enet_mii_probe() starts the PHY > >> and does the necessary calls to configure the PHY via PHY framework, > >> and loads the correct register settings into the PHY. Therefore, > >> fec_enet_mii_probe() should be called only after the PHY has been > >> reset, not before as it is now. > > > > I think this patch is related to what Florian is currently doing with > > PHY clocks. > > Which is what ? Details please.
Have you used b4 before? b4 am 20200903043947.3272453-1-f.faine...@gmail.com > > I think a better fix for the original problem is for the SMSC PHY > > driver to control the clock itself. If it clk_prepare_enables() the > > clock, it knows it will not be shut off again by the FEC run time > > power management. > > The FEC MAC is responsible for generating the clock, the PHY clock are > not part of the clock framework as far as I can tell. I'm not sure this is true. At least: https://elixir.bootlin.com/linux/latest/source/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi#L123 and there are a few more examples: imx6ul-14x14-evk.dtsi: clocks = <&clks IMX6UL_CLK_ENET_REF>; imx6ul-kontron-n6x1x-s.dtsi: clocks = <&clks IMX6UL_CLK_ENET_REF>; imx6ul-kontron-n6x1x-som-common.dtsi: clocks = <&clks IMX6UL_CLK_ENET_REF>; imx6ull-myir-mys-6ulx.dtsi: clocks = <&clks IMX6UL_CLK_ENET_REF>; imx6ul-phytec-phycore-som.dtsi: clocks = <&clks IMX6UL_CLK_ENET_REF>; Maybe it is just IMX6? Andrew
